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copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com march '10 ds792f2 low power, stereo dac w/headphone & speaker amps features ? 98 db dynamic range (a-wtd) ? 88 db thd+n ? headphone amplifier - gnd centered ? no dc-blocking capacitors required ? integrated negative voltage regulator ? 2 x 23 mw into stereo 16 @ 1.8 v ? 2 x 44 mw into stereo 16 @ 2.5v ? stereo analog input passthrough architecture ? analog input mixing ? analog passthrough with volume control ? digital signal processing engine ? bass & treble tone control, de-emphasis ? pcm input w/independent vol control ? master digital volume control and limiter ? soft-ramp & zero-cross transitions ? programmable peak-d etect and limiter ? beep generator w/full tone control ? tone selections across two octaves ? separate volume control ? programmable on and off time intervals ? continuous, periodic, one-shot beep selections class d stereo/mono speaker amplifier ? no external filter required ? high stereo output power at 10% thd+n ? 2 x 1.00 w into 8 @ 5.0 v ? 2 x 550 mw into 8 @ 3.7 v ? 2 x 230 mw into 8 @ 2.5 v ? high mono output power at 10% thd+n ? 1 x 1.90 w into 4 @ 5.0 v ? 1 x 1.00 w into 4 @ 3.7 v ? 1 x 350 mw into 4 @ 2.5 v ? direct battery powered operation ? battery level monitoring & compensation ? 81% efficiency at 800 mw ? phase-aligned pwm output reduces idle channel current ? spread spectrum modulation ? low quiescent current +1.60 v to +5.25 v battery +1.65 v to +2.63 v digital supply pulse-width modulator battery level monitoring & compensation multi-bit ? dac level shifter +1.65 v to +3.47 v interface supply control port serial audio port beep generator digital volume, mono mix, limiter, bass, treble adjust left inputs 4 3 2 1 summing amplifiers left hp/line output ground-centered amps right hp/line output +1.65 v to +2.63 v headphone supply speaker/hp switch charge pump +vhp -vhp +1.65 v to +2.63 v analog supply stereo/mono full-bridge speaker outputs class d amps + - + - i2c control reset serial audio input right inputs 4 3 2 1 cs43l22 confidential draft 3/4/10
2 ds792f2 cs43l22 confidential draft 3/4/10 system features ? 12, 24, and 27 mhz master clock support in addition to typical audio clock rates ? high performance 24-bit converters ? multi-bit delta?sigma architecture ? very low 64fs oversampling clock reduces power consumption ? low power operation ? stereo analog passthrough: 10 mw @ 1.8 v ? stereo playback: 14 mw @ 1.8 v ? variable power supplies ? 1.8 v to 2.5 v digital & analog ? 1.6 v to 5 v class d amplifier ? 1.8 v to 2.5 v headphone amplifier ? 1.8 v to 3.3 v interface logic ? power down management ? dac, passthrough amplifier, headphone amplifier, speaker amplifier ? flexible clocking options ? master or slave operation ? quarter-speed mode - (i.e. allows 8 khz fs while maintaining a flat noise floor up to 16 khz) ? 4 khz to 96 khz sample rates ? i2c tm control port operation ? headphone/speaker detection input ? pop and click suppression ? pin-compatible w/cs42l52 applications ? pda?s ? personal media players ? portable game consoles general description the cs43l22 is a highly inte grated, low power stereo dac with headphone and class d speaker amplifiers. the cs43l22 offers many features suitable for low power, porta- ble system applications. the dac output path includes a digital signal processing en- gine with various fixed function controls. tone control provides bass and treble adjustment of four selectable corner frequencies. digital volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. the dac also includes de-emphasis, limitin g functions and a beep genera- tor delivering tones selectable across a range of two full octaves. the stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. this allows a ground-centered analog output with a wide signal swing and eliminates the need for external dc-blocking capacitors. the class d stereo speaker amplifier does not require an external filter and provides the high efficiency amplification re- quired by power sensitive portable applications. the speaker amplifier may be powered directly from a battery while the in- ternal dc supply monitoring and compensation provides a constant gain level as th e battery?s voltage decays. the cs43l22 accommodates analog routing of the analog in- put signal directly to the headphone amplifier. this feature is useful in applications that ut ilize an fm tuner where audio re- covered over-the-air must be transmitted to the headphone amplifier directly. in addition to its many featur es, the cs43l22 operates from a low voltage analog and digital core making it ideal for portable systems that require extremely low power consumption in a minimal amount of space. the cs43l22 is available in a 40-pin qfn package in com- mercial (-40 to +85 c) grade. the cs43l22 customer demonstration board is also available for device evaluation and implementation suggestions. please refer to ?ordering in- formation? on page 66 for complete ordering information.
ds792f2 3 cs43l22 confidential draft 3/4/10 table of contents 1. pin descriptions ........................................................................................................... ................... 7 1.1 i/o pin characteristics ................................................................................................... .................. 8 2. typical connection diagram ................................................................................................. .... 9 3. characteristic and specificatio ns ............ ................. ................ ................ ................ ......... 10 recommended operating conditions .................................................................................. 10 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............ 10 analog output characteristics .......................................................................................... 11 analog passthrough characteristics .............................................................................. 12 pwm output characteristics ................................................................................................. 13 headphone output power characteristics ..................................................................... 14 line output voltage level characteristics . ................................................................... 15 combined dac interpolation & on-chip analog filter response ............................. 15 switching specifications - serial port .............................................................................. 16 switching specifications - i2c control port .................................................................... 17 dc electrical characteristics .............................................................................................. 18 digital interface specifications & characteris tics .................................................... 18 power consumption ............................................................................................................. ...... 19 4. applications ............................................................................................................... .................... 20 4.1 overview .................................................................................................................. ...................... 20 4.1.1 basic architecture ...................................................................................................... ........... 20 4.1.2 line inputs ............................................................................................................. ................ 20 4.1.3 line & headphone outputs ................................................................................................ ... 20 4.1.4 speaker driver outputs ......................... ......................................................................... ....... 20 4.1.5 fixed function dsp engine ............................................................................................... ... 20 4.1.6 beep generator ........... ............................................................................................... ........... 20 4.1.7 power management ........................................................................................................ ...... 20 4.2 dsp engine ............................................................................................................... ................... 21 4.2.1 beep generator ........... ............................................................................................... ........... 22 4.2.2 limiter ................................................................................................................. ................... 22 4.3 analog passthrough ........................................................................................................ ............... 24 4.4 analog outputs ............................................................................................................ .................. 25 4.5 pwm outputs ............................................................................................................... .................. 26 4.5.1 mono speaker output config uration ..................................................................................... 27 4.5.2 vp battery compensation ................................................................................................. .... 27 4.5.2.1 maintaining a desired ou tput level ........................................................................... 27 4.6 serial port clocking ...................................................................................................... ................. 29 4.7 digital interface formats ................................................................................................. ............... 30 4.7.1 dsp mode ................................................................................................................ ............. 31 4.8 initialization ............................................................................................................ ........................ 31 4.9 recommended power-up sequence ............................................................................................ 3 1 4.10 recommended power-down sequence ................ ...................................................................... 31 4.11 required initialization settings .............. ........................................................................... ............ 32 5. control port operation ..................................................................................................... ...... 33 5.1 i2c control ............................................................................................................... ....................... 33 5.1.1 memory address pointer (m ap) ............................................................................................ 34 5.1.1.1 map increment (i ncr) ............................................................................................... 34 6. register quick reference ................................................................................................... ..... 35 7. register description ....................................................................................................... ........... 37 7.1 chip i.d. and revision register (address 01h) (read only) ......................................................... 37 7.1.1 chip i.d. (read only) ................................................................................................... ......... 37 7.1.2 chip revision (read only) ............................................................................................... ..... 37 7.2 power control 1 (address 02h) ............................................................................................. ......... 37
4 ds792f2 cs43l22 confidential draft 3/4/10 7.2.1 power down .............................................................................................................. ............ 37 7.3 power control 2 (address 04h) ............................................................................................. ......... 38 7.3.1 headphone power control ................................................................................................. ... 38 7.3.2 speaker power control ................................................................................................... ...... 38 7.4 clocking control (address 05h) ............................................................................................ ......... 38 7.4.1 auto-detect ............................................................................................................. .............. 38 7.4.2 speed mode .............................................................................................................. ............ 39 7.4.3 32khz sample rate group ................................................................................................. .. 39 7.4.4 27 mhz video clock ...................................................................................................... ........ 39 7.4.5 internal mclk/lrck ratio ................................................................................................ ... 39 7.4.6 mclk divide by 2 ........................................................................................................ ......... 40 7.5 interface control 1 (address 06h) ......................................................................................... ......... 40 7.5.1 master/slave mode .................................. ..................................................................... ........ 40 7.5.2 sclk polarity ........................................................................................................... ............. 40 7.5.3 dsp mode ................................................................................................................ ............. 40 7.5.4 dac interface format .................................................................................................... ....... 40 7.5.5 audio word length ....................................................................................................... ......... 41 7.6 interface control 2 (address 07h) ......................................................................................... ......... 41 7.6.1 sclk equals mclk ........................................................................................................ ...... 41 7.6.2 speaker/headphone switch invert ........................................................................................ 4 1 7.7 passthrough x select: passa (a ddress 08h), passb (address 09h) ............................................. 42 7.7.1 passthrough input channel mapping .................................................................................... 42 7.8 analog zc and sr settings (address 0ah) ................................................................................... 42 7.8.1 ch. x analog soft ramp .................................................................................................. ...... 42 7.8.2 ch. x analog zero cross ................................................................................................. ...... 42 7.9 passthrough gang control (address 0ch) .................................................................................... 42 7.9.1 passthrough channel b=a gang control .............................................................................. 42 7.10 playback control 1 (addre ss 0dh) ......................................................................................... ...... 43 7.10.1 headphone analog gain .................................................................................................. ... 43 7.10.2 playback volume setting b=a ............... ............................................................................. 43 7.10.3 invert pcm signal polarity .................. ........................................................................... ..... 43 7.10.4 master playback mute .. ................................................................................................. ...... 43 7.11 miscellaneous controls (address 0eh) ..................................................................................... ... 44 7.11.1 passthrough analog ..... ................................................................................................ ....... 44 7.11.2 passthrough mute ....................................................................................................... ........ 44 7.11.3 freeze register s ....................................................................................................... .......... 44 7.11.4 hp/speaker de-emphasis ................................................................................................. .44 7.11.5 digital soft ramp ...... ................................................................................................ .......... 44 7.11.6 digital zero cr oss ..................................................................................................... ........... 45 7.12 playback control 2 (addre ss 0fh) ......................................................................................... ...... 45 7.12.1 headphone mute ......................................................................................................... ........ 45 7.12.2 speaker mute ........................................................................................................... ........... 45 7.12.3 speaker volume setting b=a .................... ......................................................................... .45 7.12.4 speaker channel swap ................................................................................................... .... 45 7.12.5 speaker mono control ................................................................................................... ... 46 7.12.6 speaker mute 50/50 cont rol ............................................................................................. .. 46 7.13 passthrough x volu me: passavol (address 14h) & passbvol (address 15h) ........... ......... 46 7.13.1 passthrough x vo lume ................................................................................................... ..... 46 7.14 pcmx volume: pcma (address 1ah) & pcmb (address 1bh) ................................................... 47 7.14.1 pcm channel x mute ....... .............................................................................................. ..... 47 7.14.2 pcm channel x vo lume ................................................................................................... ... 47 7.15 beep frequency & on time (address 1ch) ................................................................................ 47 7.15.1 beep frequency .................................. ....................................................................... ......... 47 7.15.2 beep on time ........................................................................................................... .......... 48
ds792f2 5 cs43l22 confidential draft 3/4/10 7.16 beep volume & off time (a ddress 1dh) ..................................................................................... 48 7.16.1 beep off time .......................................................................................................... ........... 48 7.16.2 beep volume ............................................................................................................ ........... 49 7.17 beep & tone configuration (address 1eh) .................................................................................. 49 7.17.1 beep configuration ..................................................................................................... ......... 49 7.17.2 beep mix disable ....................................................................................................... ......... 49 7.17.3 treble corner frequency ................................................................................................ .... 50 7.17.4 bass corner frequency .................................................................................................. .... 50 7.17.5 tone control enable .................................................................................................... ....... 50 7.18 tone control (address 1f h) ............................................................................................... ......... 50 7.18.1 treble gain ............................................................................................................ .............. 50 7.18.2 bass gain .............................................................................................................. .............. 51 7.19 master volume control: msta (address 20h) & mstb (address 21h) ....................................... 51 7.19.1 master volume control .................................................................................................. ...... 51 7.20 headphone volume control: hpa (address 22 h) & hpb (address 23h) .................................... 51 7.20.1 headphone volume control ............................................................................................... .51 7.21 speaker volume co ntrol: spka (address 24h) & spkb (addr ess 25h) .. ............. ............. ......... 52 7.21.1 speaker volume control ................................................................................................. .... 52 7.22 pcm channel swap (a ddress 26h) ........................................................................................... .. 52 7.22.1 pcm channel swap ....................................................................................................... ..... 52 7.23 limiter control 1, min/max thresholds (address 27h) ................................................................. 53 7.23.1 limiter maximum threshold .............................................................................................. .. 53 7.23.2 limiter cushion threshold .............................................................................................. .... 53 7.23.3 limiter soft ramp disable .............................................................................................. ..... 53 7.23.4 limiter zero cross disable ............................................................................................. ..... 54 7.24 limiter control 2, release ra te (address 28h) ........................................................................... 5 4 7.24.1 peak detect and limiter ................................................................................................ ...... 54 7.24.2 peak signal limit all channels ......................................................................................... .. 54 7.24.3 limiter release rate ................................................................................................... ........ 54 7.25 limiter attack rate (address 29h) ........................................................................................ ....... 55 7.25.1 limiter attack rate .................................................................................................... .......... 55 7.26 status (address 2eh) (read only) ......................................................................................... ..... 55 7.26.1 serial port clock error (read only) ....... ............................................................................. 55 7.26.2 dsp engine overflow (read only) ..................................................................................... 55 7.26.3 pcmx overflow (read only) .............................................................................................. .56 7.27 battery compensation (addre ss 2fh) ....................................................................................... ... 56 7.27.1 battery compensation ................................................................................................... ...... 56 7.27.2 vp monitor ............................................................................................................. .............. 56 7.27.3 vp reference ........................................................................................................... ........... 57 7.28 vp battery level (address 30h) (read only) . ............................................................................. 5 7 7.28.1 vp voltage level (read only) ........................................................................................... .57 7.29 speaker status (address 31h) (read only) ... ............................................................................. 5 7 7.29.1 speaker current load status (read only) ......................................................................... 57 7.29.2 spkr/hp pin status (read on ly) ............. ................. ................ ................ ................ ......... 58 7.30 charge pump frequency (address 34h) ..................................................................................... 5 8 7.30.1 charge pump frequency .......................... ........................................................................ .. 58 8. analog performance plots ................................................................................................... .59 8.1 headphone thd+n versus output power plots ............................................................................ 59 9. example system clock frequenc ies .......... ................. ................ ................ ................ ......... 61 9.1 auto detect enabled .................................................................................................... ............... 61 9.2 auto detect disabled .................................................................................................... ............... 61 10. pcb layout considerations ................................................................................................. .. 62 10.1 power supply, grou nding .................................................................................................. .......... 62 10.2 qfn thermal pad ........... ............................................................................................... .............. 62
6 ds792f2 cs43l22 confidential draft 3/4/10 11. digital filter plots ...................................................................................................... ............. 63 12. parameter definitions ..................................................................................................... ......... 64 13. package dimensions ........................................................................................................ .......... 65 thermal characteristics ....................................................................................................... .. 65 14. ordering information ...................................................................................................... ........ 66 15. references ................................................................................................................ .................... 66 16. revision history .......................................................................................................... ................ 66 list of figures figure 1. typical connection diagram ............ .............................................................................. .............. 9 figure 2. headphone output test load .......................................................................................... .......... 14 figure 3. serial audio interface timing ....................................................................................... .............. 16 figure 4. control port timing - i2c ............... ............................................................................ ................. 17 figure 5. dsp engine signal flow .............................................................................................. .............. 21 figure 6. beep configuration options ............. ............................................................................. ............. 22 figure 7. peak detect & limiter ............................................................................................... ................. 23 figure 8. analog passthrough signal flow ...................................................................................... ......... 24 figure 9. analog outputs ...................................................................................................... .................... 25 figure 10. pwm output stage ................................................................................................... ............... 26 figure 11. battery compensation ...................... ......................................................................... .............. 28 figure 12. i2s format ......................................................................................................... ....................... 30 figure 13. left-justified format .............................................................................................. .................. 30 figure 14. right-justified format\ ............................................................................................ ................. 30 figure 15. dsp mode format) .. ................................................................................................. ............... 31 figure 16. control port timing, i2c write ..................................................................................... ............. 33 figure 17. control port timing, i2c read ...................................................................................... ............ 33 figure 18. thd+n vs. output po wer per channel at 1.8 v (16 load) ................................................... 59 figure 19. thd+n vs. output po wer per channel at 2.5 v (16 load) ................................................... 59 figure 20. thd+n vs. output po wer per channel at 1.8 v (32 load) ................................................... 60 figure 21. thd+n vs. output po wer per channel at 2.5 v (32 load) ................................................... 60 figure 22. passband ripple .................................................................................................... .................. 63 figure 23. stopband ........................................................................................................... ....................... 63 figure 24. dac transition band ................................................................................................ ............... 63 figure 25. transition band (det ail) ........................................................................................... ................ 63
ds792f2 7 cs43l22 confidential draft 3/4/10 1. pin descriptions pin name # pin description sda 1 serial control data ( input / output ) - sda is a data i/o in i2c mode. scl 2 serial control port clock ( input ) - serial clock for th e serial control port. ad0 3 address bit 0 (i2c) ( input ) - ad0 is a chip address pin in i2c mode. spkr_outa+ spkr_outa- spkr_outb+ spkr_outb- 4 6 7 9 pwm speaker output ( output ) - full-bridge amplified pwm speaker outputs. vp 5 8 power for pwm drivers ( input ) - power supply for the pwm output driver stages. -vhpfilt 10 inverting charge pump filter connection (output) - power supply from the inverting charge pump that provides the negative ra il for the headphone/line amplifiers. flyn 11 charge pump cap negative node (output) - negative node for the inverting charge pump?s fly- ing capacitor. flyp 12 charge pump cap positive node (output) - positive node for the inverting charge pump?s flying capacitor. +vhp 13 positive analog power for headphone ( input ) - positive voltage rail and power for the internal headphone amplifiers and inverting charge pump. hp/line_outb, a 14,15 headphone/line audio output ( output ) - stereo headphone or line level analog outputs. va 16 analog power ( input ) - positive power for the internal analog section. 12 11 13 14 15 16 17 18 19 20 29 30 28 27 26 25 24 23 22 21 39 40 38 37 36 35 34 33 32 31 2 1 3 4 5 6 7 8 9 10 gnd/thermal pad tsto mclk sclk sdin sda lrck flyn +vhp hp/line_outb hp/line_outa vq tsto ain4a ain2a ad0 spkr_outa+ vp vp vd spkr_outb- -vhpfilt ain4b ain1b ain2b afiltb ain3b afilta ain1a ain3a spkr_outb+ scl dgnd spkr_outa- flyp va agnd filt+ reset vl spkr/hp top-down (through-package) view 40-pin qfn package
8 ds792f2 cs43l22 confidential draft 3/4/10 1.1 i/o pin characteristics input and output levels and associated power supply voltage are shown in the table below. logic levels should not exceed the corresponding power supply voltage. agnd 17 analog ground ( input ) - ground reference for the internal analog section. filt+ 18 positive voltage reference (output) - filter connection for the internal sampling circuits. vq 19 quiescent voltage ( output ) - filter connection for the internal quiescent voltage. tsto 20,36 test out ( output ) - this pin is an output used for test pur poses only and must be left ?floating? (no connection external to the pin). ain4a,b ain3a,b ain2a,b ain1a,b 21,22 23,24 25,26 29,30 line-level analog inputs ( input ) - single-ended stereo line-level analog inputs. afilta,afiltb 27,28 anti-alias filter connection (output) - anti-alias filter connection for analog passthrough mode. spkr/hp 31 speaker/headphone switch ( input ) - powers down the left and/or right channel of the speaker and/or headphone outputs. reset 32 reset ( input ) - the device enters a low power mode when this pin is driven low. vl 33 digital interface power ( input ) - determines the required signal level for the serial audio inter- face and host control port. vd 34 digital power ( input ) - positive power for the internal digital section. dgnd 35 digital ground ( input ) - ground reference for the internal digital section. mclk 37 master clock ( input ) - clock source for the delta-sigma modulators. sclk 38 serial clock ( input/output ) - serial clock for the serial audio interface. sdin 39 serial audio data input ( input ) - input for two?s complement serial audio data. lrck 40 left right clock ( input/output ) - determines which channel, left or right, is currently active on the serial audio data line. gnd/thermal pad - ground reference for pwm power fets and charge pump; thermal relief pad for optimized heat dissipation. power supply pin name i/o internal connections driver receiver vl reset input - - 1.65 v - 3.47 v, with hysteresis ad0 input - - 1.65 v - 3.47 v, with hysteresis scl input - - 1.65 v - 3.47 v, with hysteresis sda input/ output - 1.65 v - 3.47 v, cmos/open drain 1.65 v - 3.47 v, with hysteresis mclk input - - 1.65 v - 3.47 v lrck input/ output weak pull-up (~1 m ) 1.65 v - 3.47 v, cmos 1.65 v - 3.47 v sclk input/ output weak pull-up (~1 m ) 1.65 v - 3.47 v, cmos 1.65 v - 3.47 v sdin input - - 1.65 v - 3.47 v va spkr/hp input - - 1.65 v - 2.63 v vp spkr_outa+ output - 1.6 v - 5.25 v power mosfet - spkr_outa- output - 1.6 v - 5.25 v power mosfet - spkr_outb+ output - 1.6 v - 5.25 v power mosfet - spkr_outb- output - 1.6 v - 5.25 v power mosfet -
ds792f2 9 cs43l22 confidential draft 3/4/10 2. typical conn ection diagram note 3 note 2 note 1 1 f +1.8 v to +2.5 v 0.1 f 1 f dgnd vl 0.1 f +1.8 v to +3.3 v scl sda reset 2 k lrck digital audio processor mclk sclk vd sdin cs43l22 2 k +1.8 v to +2.5 v hp/line_outb hp/line_outa ain1a left 1 100 k 100 ain1b right 1 0.1 f va headphone out left & right line level out left & right flyp flyn -vhpfilt 51.1 0.022 f 100 k 100 spkr_outa+ spkr_outa- spkr/hp 51.1 0.022 f 1 f 1 f 0.1 f +vhp 1 f vq agnd * capacitors must be c0g or equivalent 1 f ** ** see note 4 spkr_outb+ spkr_outb- 1 f vp vp +1.6 v to +5 v stereo speakers ain2a left 2 100 k 100 ain2b right 2 100 k 100 1 f 1 f 0.1 f 0.1 f analog input 1 analog input 2 10 f 47 k notes: 1. recommended values for the default charge pump switching frequency. the required capacitance follows an inverse relationship with the charge pump?s switching frequency. when increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. 2. larger capacitance reduces the ripple on the internal amplifier?s supply. this may re duce the distortion at higher output power levels. 3. additional bulk capacitance may be added to improve psrr at low frequencies. 4. series resistance in the path of the power supplies must be avoided. any voltage drop on vhp will directly impact the negative charge pump supply (-vhpfilt) and clip the audio output. ain3a left 3 100 k 100 ain3b right 3 100 k 100 1 f 1 f analog input 3 ain4a left 4 100 k 100 ain4b right 4 100 k 100 1 f 1 f analog input 4 filt+ 10 f 150 pf 150 pf afilta afiltb ** low esr, x7r/x5r dielectric capacitors. ** ** ** ** ** ** ** ** * * tsto tsto ad0 figure 1. typical connection diagram
10 ds792f2 cs43l22 confidential draft 3/4/10 3. characteristic and specifications recommended operating conditions agnd=dgnd=0 v, all voltages with respect to ground. absolute maximum ratings agnd = dgnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. any pin except supplies. transient currents of up to 100 ma on the analog input pins will not cause scr latch-up. 2. the maximum over/under voltage is limited by the input current. parameters symbol min max units dc power supply analog va 1.65 2.63 v headphone amplifier +vhp 1.65 2.63 v speaker amplifier vp 1.60 5.25 v digital vd 1.65 2.63 v serial/control port interface vl 1.65 3.47 v ambient temperature commercial t a -40 +85 c parameters symbol min max units dc power supply analog speaker digital serial/control port interface va, vhp vp vd vl -0.3 -0.3 -0.3 -0.3 3.0 5.5 3.0 4.0 v v v v input current (note 1) i in -10ma analog input voltage (note 2) v in agnd-0.7 va+0.7 v external voltage applied to analog input (note 2) v in agnd-0.3 va+0.3 v external voltage applied to analog output v in -vhp - 0.3 +vhp + 0.3 v external voltage applied to digital input (note 2) v ind -0.3 vl+ 0.3 v ambient operating temperature (power applied) t a -50 +115 c storage temperature t stg -65 +150 c
ds792f2 11 cs43l22 confidential draft 3/4/10 analog output cha racteristics test conditions (unless other wise specified): input test signal is a fu ll-scale 997 hz sine wave; all supplies = va; t a = +25 c; sample frequency = 48 khz; measurement bandwidth is 20 hz to 20 khz; test load r l = 10 k , c l = 10 pf for the line output (see figure 2 ); test load r l = 16 , c l = 10 pf (see figure 2 ) for the headphone output; hp_gain[2:0] = 011. 3. one (least-significant bit) lsb of triangular pdf dither is added to data. 4. full-scale output voltage and power is determ ined by the gain setting, g, in register ?headphone analog gain? on page 43 . high gain settings at certain va and vhp su pply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in figures 18 - 21 on page 60 . va = 2.5 v va = 1.8 v parameters (note 3) min typ max min typ max unit r l = 10 k dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -80 - -29 - - - - - - - - - -88 -72 -32 -88 -70 -30 -82 - -26 - - - db db db db db db r l = 16 dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -69 - -29 - - - - - - - - - -75 -72 -32 -75 -70 -30 -69 - -26 - - - db db db db db db other characteristics for r l = 16 or 10 k output parameters modulation index (mi) (note 4) analog gain multiplier (g) - - 0.6787 0.6047 - - - - 0.6787 0.6047 - - v/v v/v full-scale output voltage (2?g?mi?va) (note 4) refer to table ?headphone output power characteris- tics? on page 14 vpp full-scale output power (note 4) refer to table ?headphone output power characteristics? on page 14 interchannel isolation (1 khz) 16 10 k - - 80 95 - - - - 80 93 - - db db speaker amp to hp amp isolation - 80 - - 80 - db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c ac-load resistance (r l ) (note 5) 16 - - 16 - - load capacitance (c l ) (note 5) - - 150 - - 150 pf
12 ds792f2 cs43l22 confidential draft 3/4/10 5. see figure 2 . r l and c l reflect the recommended minimum resi stance and maximum capacitance re- quired for the internal op-amp's stability and signal integrity. in this circuit topology, c l will effectively move the band-limiting pole of the amp in the outp ut stage. increasing this value beyond the recom- mended 150 pf can cause the internal op-amp to become unstable. analog passthrough characteristics test conditions (unless otherwise specified): input sine wave (re lative to full-scale): 1 khz through passive input filter; passthrough amplifier and hp/line gain = 0 db; all supplies = va; t a = +25 c; sample frequency = 48 khz; measurement bandwidth is 20 hz to 20 khz. va = 2.5 v va = 1.8 v parameters min typ max min typ max unit analog in to hp/line amp r l = 10 k dynamic range a-weighted unweighted - - -96 -93 - - - - -94 -91 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -70 -73 -33 - - - - - - -70 -71 -31 - - - db db db full-scale input voltage - 0.91?va - - 0.91?va - vpp full-scale output voltage - 0.84?va - - 0.84?va - vpp passband ripple - 0/-0.3 - - 0/-0.3 - db r l = 16 dynamic range a-weighted unweighted - - -96 -93 - - - - -94 -91 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -70 -73 -33 - - - - - - -70 -71 -31 - - - db db db full-scale input voltage - 0.91?va - - 0.91?va - vpp full-scale output voltage - 0.84?va - - 0.84?va - vpp output power - 32 - - 17 - mw passband ripple - 0/-0.3 - - 0/-0.3 - db
ds792f2 13 cs43l22 confidential draft 3/4/10 pwm output characteristics test conditions (unless otherwise specified) : input test signal is a full scale 997 hz signal; mclk = 12.2880 mhz; measurement bandwidth is 20 hz to 20 khz; sample frequency = 48 khz; test load r l = 8 for stereo full-bridge, r l = 4 for mono parallel full-bridge; vd = vl = va = vhp = 1.8v; pwm modula tion index of 0.85; pwm switch rate = 384 khz. parameters (note 7) symbol conditions min typ max units vp = 5.0 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 1.00 0.80 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 1.90 1.50 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.8w - 0.52 - % mono parallel full-bridge p o = -3 dbfs = 0.75 w p o = 0 dbfs = 1.5 w - - 0.10 0.50 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db vp = 3.7 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 0.55 0.45 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 1.00 0.84 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.43 w - 0.54 - % mono parallel full-bridge p o = -3 dbfs = 0.41 w p o = 0 dbfs = 0.81 w - - 0.09 0.45 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 95 92 - - db db vp =2.5 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 0.23 0.19 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 0.44 0.35 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.18 w - 0.50 - % mono parallel full-bridge p o = -3 dbfs = 0.17 w p o = 0 dbfs = 0.35 w - - 0.08 0.43 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 94 91 - - db db mosfet on resistance r ds(on) vp = 5.0v, i d = 0.5 a - 600 - m mosfet on resistance r ds(on) vp = 3.7v, i d = 0.5 a - 640 - m
14 ds792f2 cs43l22 confidential draft 3/4/10 6. the pwm driver should be used in captive speaker systems only. 7. optimal pwm performance is achieved when mclk > 12 mhz. headphone output po wer characteristics test conditions (unless otherwise specifi ed): input test signal is a full-scale 997 hz sine wave; sample frequency = 48 khz; measurement bandwidth is 20 hz to 20 khz; test load r l = 16 , c l = 10 pf (see figure 2 ); ?required initialization settings? on page 32 written on power up. 8. vhp settings lower than va reduces the headroom of the headphone amplifier. as a result, the dac may not achieve the full thd+n performance at full-scale output voltage and power. mosfet on resistance r ds(on) vp = 2.5v, i d = 0.5 a - 760 - m efficiency vp = 5.0 v, p o = 2 x 0.8 w, r l = 8 -81-% output operating peak current i pc --1.5a vp input current during reset i vp reset , pin 32, is held low -0.85.0a parameters va = 2.5v min typ max va = 1.8v min typ max unit aoutx power into r l = 16 hp_gain[2:0] analog gain (g) vhp 000 0.3959 1.8 v - 14 - - 7 - mw rms 2.5 v - 14 - - 7 - mw rms 001 0.4571 1.8 v - 19 - - 10 - mw rms 2.5 v - 19 - - 10 - mw rms 010 0.5111 1.8 v - 23 - - 12 - mw rms 2.5 v - 23 - - 12 - mw rms 011 (default) 0.6047 1.8 v (note 8) - 17 - mw rms 2.5 v - 32 - - 17 - mw rms 100 0.7099 1.8 v (note 8) - 23 - mw rms 2.5 v - 44 - - 23 - mw rms 101 0.8399 1.8 v (note 4) see figure 18 on page 59 mw rms 2.5 v - 32 - mw rms 110 1.0000 1.8 v ( note 4 , 8 ) see figures 18 and 19 on page 59 mw rms 2.5 v mw rms 111 1.1430 1.8 v mw rms 2.5 v mw rms parameters (note 7) symbol conditions min typ max units aoutx agnd r l c l 0.022 f 51
ds792f2 15 cs43l22 confidential draft 3/4/10 line output voltage level characteristics test conditions (unless otherwise specifi ed): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 20 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k , c l = 10 pf (see figure 2 ); ?required initialization settings? on page 32 written on power up. combined dac interpol ation & on-chip anal og filter response 9. response is clock dependent and will scale wi th fs. note that the response plots ( figures 22 and 25 on page 63 ) have been normalized to fs and can be de-normaliz ed by multiplying the x-axis scale by fs. 10. measurement bandwidth is from stopband to 3 fs. parameters va = 2.5v min typ max va = 1.8v min typ max unit aoutx voltage into r l = 10 k hp_gain[2:0] analog gain (g) vhp 000 0.3959 1.8 v - 1.34 - - 0.97 - v pp 2.5 v - 1.34 - - 0.97 - v pp 001 0.4571 1.8 v - 1.55 - - 1.12 - v pp 2.5 v - 1.55 - - 1.12 - v pp 010 0.5111 1.8 v - 1.73 - - 1.25 - v pp 2.5 v - 1.73 - - 1.25 - v pp 011 (default) 0.6047 1.8 v - 2.05 - 1.41 1.48 1.55 v pp 2.5 v 1.95 2.05 2.15 - 1.48 - v pp 100 0.7099 1.8 v - 2.41 - - 1.73 - v pp 2.5 v - 2.41 - - 1.73 - v pp 101 0.8399 1.8 v - 2.85 - 2.05 v pp 2.5 v - 2.85 - - 2.05 - v pp 110 1.0000 1.8 v - 3.39 - - 2.44 - v pp 2.5 v - 3.39 - - 2.44 - v pp 111 1.1430 1.8 v (see (note 8) 2.79 v pp 2.5 v - 3.88 - - 2.79 - v pp parameters (note 9) min typ max unit frequency response 10 hz to 20 khz -0.01 - +0.08 db passband to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs stopband 0.5465 - - fs stopband attenuation (note 10) 50 - - db group delay - 9/fs - s de-emphasis error fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db
16 ds792f2 cs43l22 confidential draft 3/4/10 switching specificat ions - serial port inputs: logic 0 = dgnd; logic 1 = vl. 11. after powering up the cs43l22, reset should be held low after the power supplies and clocks are settled. 12. see ?example system clock frequencies? on page 61 for typical mclk frequencies. parameters symbol min max units reset pin low pulse width (note 11) 1-ms mclk frequency (note 12) (see ?serial port clock- ing? on page 29 ) mhz mclk duty cycle 45 55 % slave mode sample rate (lrck) f s (see ?serial port clock- ing? on page 29 ) khz lrck duty cycle 45 55 % sclk frequency 1/t p -64?f s hz sclk duty cycle 45 55 % lrck setup time before sclk rising edge t s(lk-sk) 40 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns master mode sample rate (lrck) f s (see ?serial port clock- ing? on page 29 ) hz lrck duty cycle 45 55 % sclk frequency sclk=mclk mode 1/t p - 12.0000 mhz mclk=12.0000 mhz 1/t p -68?f s hz all other modes 1/t p -64?f s hz sclk duty cycle 45 55 % sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns // // // // // // t s(sd-sk) msb msb-1 lrck sclk sdin t s(lk-sk) t p t h figure 3. serial audio interface timing
ds792f2 17 cs43l22 confidential draft 3/4/10 switching specificatio ns - i2c control port inputs: logic 0 = dgnd; logic 1 = v; sda c l =30pf. 13. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameters symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 550 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 13) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs reset figure 4. control port timing - i2c
18 ds792f2 cs43l22 confidential draft 3/4/10 dc electrical characteristics agnd = 0 v; all voltages with respect to ground. 14. valid with the recommended capacitor values on filt+ and vq. increasing the capacitance will also increase the psrr. digital interface specific ations & characteristics 15. see ?i/o pin characteristics? on page 8 for serial and control port power rails. parameters min typ max units vq characteristics nominal voltage output impedance dc current source/sink - - - 0.5?va 23 - - - 1 v k a power supply rejection ratio characteristics psrr @ 1 khz (note 14) dac (hp & line amps) - 60 - db psrr @ 60 hz (note 14) dac (hp & line amps) - 60 - db psrr @ 217 hz full-bridge pwm outputs - 56 - db parameters (note 15) symbol min max units input leakage current i in -10 a input capacitance -10pf 1.8 v - 3.3 v logic high-level output voltage (i oh = -100 a) v oh vl - 0.2 - v low-level output voltage (i ol = 100 a) v ol -0.2v high-level input voltage vl = 1.65 v vl = 1.8 v vl = 2.0 v vl > 2.0 v v ih 0.85?vl 0.77?vl 0.68?vl 0.65?vl - - - - v v v v low-level input voltage v il - 0.30?vl v
ds792f2 19 cs43l22 confidential draft 3/4/10 power consumption see (note 16) 16. unless otherwise noted, test conditions are as follows: all zeros input, slave mode, sample rate = 48 khz; no load. digital (vd) and logic (vl) supply current will vary depending on speed mode and master/slave operation. ?required initialization settings? on page 32 written on power up. 17. reset pin 25 held lo, all clocks and data lines are held lo. 18. reset pin 25 held hi, all clocks and data lines are held hi. 19. vl current will slightly in crease in master mode. register settings typical current (ma) operation 02h 04h pdn[7:0] pdn_hpb[1:0] pdn_hpa[1:0] pdn_spkb[1:0] pdn_spka[1:0] v i vhp i va i vd i vl vl=3.3v (note 19) i vp vp=3.7v total power (mw rms ) 1 off (note 17) x x x x x 1.8 0.00 0.00 0.00 0.00 0.00 0.00 2.5 0.00 0.00 0.00 0.00 2 standby (note 18) 0x9f x x x x 1.8 0.00 0.00 0.01 0.00 0.00 0.02 2.5 0.00 0.00 0.02 0.05 3 stereo passthrough to headphone 0x9e 10 10 11 11 1.8 2.79 1.91 1.06 0.01 0.00 10.39 2.5 3.18 2.14 1.81 17.85 4 mono playback to headphone 0x9e 10 11 11 11 1.8 1.59 1.99 2.72 0.01 0.00 11.36 2.5 2.07 2.62 4.27 22.43 5 stereo playback to headphone 0x9e 10 10 11 11 1.8 2.77 2.00 2.91 0.01 0.00 13.84 2.5 3.27 2.63 4.28 25.48 6 mono playback to speaker 0x9e 11 11 10 10 1.8 0.00 0.20 4.42 0.01 1.00 12.05 2.5 0.00 0.22 6.77 21.21 7 stereo playback to speaker 0x9e 11 11 10 10 1.8 0.00 0.20 4.38 0.01 1.00 11.98 2.5 0.00 0.22 6.80 21.28
20 ds792f2 cs43l22 confidential draft 3/4/10 4. applications 4.1 overview 4.1.1 basic architecture the cs43l22 is a highly integrated, low power, 24-bit audio dac comprised of a digital signal processing engine, headphone amplifiers, a digital pwm modulator and two full-bridge power back-ends. other fea- tures include battery level monitoring and compensation and temperature monitoring. the dac is de- signed using multi-bit delta-sigma techniques and o perates at an oversampling ratio of 128fs, where fs is equal to the system sample rate. the pwm modulator operates at a fixed frequency of 384 khz. the power mosfets are configured for either stereo full-bridge or mono parallel full bridge output. the dac operates in one of four sample rate speed modes: quarter, half, single and double. it ac cepts and is capable of generating serial port clocks (sclk, lrck) derived from an input master clock (mclk). 4.1.2 line inputs 4 pairs of stereo analog inputs are provided for applications that require analog passthrough directly to the hp/line amplifiers. this analog i nput portion allows selection from and configuration of multiple com- binations of these stereo sources. 4.1.3 line & headphone outputs the analog output portion of the cs43l22 includes a headphone amplifier capable of driving headphone and line-level loads. an on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. this eliminat es the need for large dc-blocking capacitors and al- lows the amplifier to deliver more power to headphone loads at lower supply voltages. 4.1.4 speaker driver outputs the class d power amplifiers drive 8 (stereo) and 4 (mono) speakers directly, without the need for an external filter. the power mosfets are powered dire ctly from a battery eliminating the efficiency loss associated with an external regulator. battery leve l monitoring and compensation maintains a steady out- put as battery levels fall. a temperature monitor co ntinually measures the die temperature and registers when predefined thresholds are exceeded. note : the cs43l22 should only be used in captive speaker systems where the outputs are permanently tied to the speaker terminals. 4.1.5 fixed func tion dsp engine the fixed-function digital signal processing engine processes the pcm serial input data. independent vol- ume control, left/right channel swaps, mono mixes, tone control and limiting functions also comprise the dsp engine. 4.1.6 beep generator the beep generator delivers tones at select frequenc ies across approximately two octave major scales. with independent volume control, beeps may be confi gured to occur continuously , periodically, or at sin- gle time intervals. 4.1.7 power management two control registers provide independent power-do wn control of the dac, headphone and speaker out- put blocks in the cs43l22 allowin g operation in select applicatio ns with minimal power consumption.
ds792f2 21 cs43l22 confidential draft 3/4/10 4.2 dsp engine referenced control register location dsp deemph ............................. pcmxmute ........................ pcmxvol[6:0] .................... inv_pcmx........................... pcmxswap[1:0] ................. mstxvol[7:0]..................... mstxmute......................... digsft ............................... digzc ................................. plybckb=a........................ tc_en................................. bass_cf[1:0] ..................... treb_cf[1:0] ..................... bass[3:0]............................ treb[3:0]............................ limit ................................... limsrdis ........................... limzcdis............................ lmax[2:0]............................ cush[2:0] ........................... limarate[7:0].................... limrrate[7:0] ................... ?hp/speaker de-emphasis? on page 44 ?pcm channel x mute? on page 47 ?pcm channel x volume? on page 47 ?invert pcm signal polarity? on page 43 ?pcm channel swap? on page 52 ?master volume control? on page 51 ?master playback mute? on page 43 ?digital soft ramp? on page 44 ?digital zero cross? on page 45 ?playback volume setting b=a? on page 43 ?tone control enable? on page 50 ?bass corner frequency? on page 50 ?treble corner frequency? on page 50 ?bass gain? on page 51 ?treble gain? on page 50 ?peak detect and limiter? on page 54 ?limiter soft ramp disable? on page 53 ?limiter zero cross disable? on page 54 ?limiter maximum threshold? on page 53 ?limiter cushion threshold? on page 53 ?limiter attack rate? on page 55 ?limiter release rate? on page 54 beep generator bass/ treble/ control vol peak detect limiter chnl vol. settings demph vol vol +12db/-102db 0.5db steps mstavol[7:0] mstbvol[7:0] +12db/-51.5db 0.5db steps pcmamute pcmbmute pcmavol[6:0] pcmbvol[6:0] 0db/-50db 2.0db steps bpvol[4:0] deemph tc_en bass_cf[1:0] treb_cf[1:0] bass[3:0] treb[3:0] +12.0db/-10.5db 1.5db steps fixed function dsp mstamute mstbmute digsft digzc plybckb=a limarate[7:0] limrrate[7:0] lmax[2:0] cush[2:0] limsrdis limzcdis limit pcmaswap[1:0] pcmbswap[1:0] pcm serial interface offtime[2:0] ontime[3:0] freq[3:0] beep[1:0] beepmixdis channel swap inv_pcma inv_pcmb pwm modulator dac figure 5. dsp engine signal flow
22 ds792f2 cs43l22 confidential draft 3/4/10 4.2.1 beep generator the beep generator generates audio frequencies acro ss approximately two octave major scales. it offers three modes of operation: continuous, multiple and si ngle (one-shot) beeps. sixteen on and eight off times are available. note: the beep is generated before the limiter and may affect desired limiting pe rformance. if the lim- iter function is used, it may be required to set the b eep volume sufficiently below the threshold to prevent the peak detect from triggering. sinc e the master volume control, mstx vol[7:0], will affect the beep vol- ume, dac volume may alternatively be controlled using the pcmxvol[6:0] bits. 4.2.2 limiter when enabled, the limiter monitors the digital input signal before the dac and pwm modulators, detects when levels exceed the maximum threshold settings and lowers the master volume at a programmable attack rate below the maximum threshold. when the input signal level falls below the maximum threshold, the aout volume returns to its original level set in the master vo lume control register at a programmable release rate. attack and release rates are affected by the dac soft ramp/zero cross settings and sample rate, fs. limiter soft ramp and zero cross dependency may be independently enabled/disabled. notes: 1. recommended settings : best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. the min bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. 2. the limiter maintains the output signal between the cush and max thresholds. as the digital input signal level changes, the level-co ntrolled output may not always be th e same but will always fall within referenced control register location mstxvol[7:0]..................... pcmxvol[6:0] .................... offtime[2:0] ..................... ontime[3:0] ....................... freq[3:0] ........................... beep[1:0]............................ beepmixdis ...................... bpvol[4:0] ......................... ?master volume control: msta (address 20h) & mstb (address 21h)? on page 51 ?pcmx volume: pcma (address 1ah) & pcmb (address 1bh)? on page 47 ?beep off time? on page 48 ?beep on time? on page 48 ?beep frequency? on page 47 ?beep configuration? on page 49 ?beep mix disable? on page 49 ?beep volume? on page 49 freq[3:0] ... bpvol[4:0] ontime[3:0] offtime[2:0] beep[1:0] = '01' beep[1:0] = '10' beep[1:0] = '11' single-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime. beep must be cleared and set for additional beeps. multi-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime and turns off for the duration of offtime. on and off cycles are repeated until beep is cleared. continuous beep : beep turns on at a configurable frequency (freq) and volume (bpvol) and remains on until beep is cleared. figure 6. beep configuration options
ds792f2 23 cs43l22 confidential draft 3/4/10 the thresholds. referenced contro l register location limiter controls ................... master volume control........ ?limiter control 2, release rate (address 28h)? on page 54 , ?limiter attack rate (address 29h)? on page 55 ?master volume control: msta (address 20h) & mstb (address 21h)? on page 51 max[2:0] output (after limiter) input rrate[5:0] arate[5:0] volume limiter cush[2:0] attack/release sound cushion max[2:0] figure 7. peak detect & limiter
24 ds792f2 cs43l22 confidential draft 3/4/10 4.3 analog passthrough the cs43l22 accommodates analog routing of the analog input signal directly to the headphone amplifiers by using the passthrux mux. this feat ure is useful in applications th at utilize an fm tuner where audio recovered over-the-air must be transmitted to the headphone amplifier directly. this analog passthrough path reduces power consumption and is immune to modulator switching noise that could interfere with some tuners. four analog input ch annels can be chosen or summed by using the passxsel bits as shown in figure 8 to provide input to the cs43l22 when in analog passthrough mode. a pair of passthrough amplifiers can be used to mute and apply gain to the input signals. referenced control register location analog front end passb=a ............................ anlgsftx .......................... anlgzcx ............................ passxsel4,3,2,1 ................ passxmute ....................... passxvol[7:0] ................... passthrux........................ ?passthrough channel b=a gang control? on page 42 ?ch. x analog soft ramp? on page 42 ?ch. x analog zero cross? on page 42 ?passthrough input channel mapping? on page 42 ?passthrough mute? on page 44 ?passthrough x volume? on page 46 ?passthrough analog? on page 44 ain4b ain1b ain2b ain3b analog pass thru to headphone amplifier mux ain4a ain1a ain2a ain3a analog passthru amplifiers anlgsftb anlggzcb passb=a passbmute passbvol[7:0] +12db/-60db 0.5 db steps anlgsfta anlggzca passb=a passamute passavol[7:0] +12db/-60db 0.5 db steps passasel[4:1] passbsel[4:1] dac a output dac b output passthrua passthrub figure 8. analog passthrough signal flow
ds792f2 25 cs43l22 confidential draft 3/4/10 4.4 analog outputs referenced control register location analog output hpxmute ........................... hpxvol[7:0] ....................... pdn_hpx[1:0] ..................... hpgain[2:0]........................ passthrux ....................... passxmute ....................... passxvol[7:0] ................... chgfreq .......................... ?headphone mute? on page 45 ?headphone volume control? on page 51 ?headphone power control? on page 38 ?headphone analog gain? on page 43 ?passthrough analog? on page 44 ?passthrough mute? on page 44 ?passthrough x volume? on page 46 ?charge pump frequency? on page 58 dac chgfreq[3:0] hpgain[2:0] vol vol analog passthru input signal hpamute hpbmute hpa_vol[7:0] hpb_vol[7:0] +0db/-102db 0.5db steps passamute passbmute passavol[7:0] passbvol[70] +12db/-60db 0.5db steps passthrua passthrub pdn_hpa[1:0] pdn_hpb[1:0] a b from dsp engine hp/line outputs charge pump figure 9. analog outputs
26 ds792f2 cs43l22 confidential draft 3/4/10 4.5 pwm outputs note: the pwm speaker amplifiers sh ould not be used in the 384x mclk modes (18.4320 and 16.9344 mhz). referenced contro l register location pwm control spkxmute ......................... mute50/50 ......................... spkmono .......................... spkxvol[7:0] ..................... spkswap........................... spkb=a .............................. battcmp ........................... vpref[3:0] ......................... vplvl[7:0] .......................... pdn_spkx[1:0]................... spkxshrt.......................... ?speaker mute? on page 45 ?speaker mute 50/50 control? on page 46 ?speaker mono control? on page 46 ?speaker volume control? on page 52 ?speaker channel swap? on page 45 ?speaker volume setting b=a? on page 45 ?battery compensation? on page 56 ?vp reference? on page 57 ?vp voltage level (read only)? on page 57 ?speaker power control? on page 38 ?speaker current load status (read only)? on page 57 vol pwm modulator a spkamute spkbmute mute50/50 spkmono spkswap spkb=a spkavol[7:0] spkbvol[7:0] +0db/-102db 0.5db steps pdn_spka[1:0] pdn_spkb[1:0] short circuit spkashrt battery compensation battcmp vpref[3:0] vplvl[7:0] spkbshrt + - + - gate drive from dsp engine speaker outputs b figure 10. pwm output stage
ds792f2 27 cs43l22 confidential draft 3/4/10 4.5.1 mono speaker output configuration the cs43l22 accommodates a stereo as well as a mo no speaker output configuration. in mono mode the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speak- er. refer to the table below for pin mapping in mono configuration. 4.5.2 vp battery compensation the cs43l22 provides the option to maintain a desired power output level, independent of the vp supply. when enabled, this feature works by monitoring the voltage on the vp supply and reducing the attenua- tion on the speaker outputs when vp voltage levels fall. note: the internal adc that monitors the vp supply op erates from the va supply. calculations are based on typical va levels of 1.8 v and 2.5 v using the vpref bits. 4.5.2.1 maintaining a desired output level using spkxvol, the speaker output le vel must first be attenuated by th e decibel equivalent of the expect- ed vp supply range (max relative to min). the cs43l22 then gradually reduces the attenuation as the vp supply drops from its maximum level, maintaining a nearly constant power output. compensation example 1 (vp battery supply ranges from 4.5 v to 3.0 v) 1. set speaker attenuatio n (spkxvol) to -3.5 db. the vp supply changes ~3.5 db. 2. set the reference vp supply (vpref) to 4.5 v. 3. enable battery compensation (battcmp). the cs43l22 automatically adjusts the output level as the battery discharges. compensation example 2 (vp battery supply ranges from 5.0 v to 1.6 v) 1. set speaker attenuatio n (spkxvol) to -10 db. the vp supply changes ~9.9 db. 2. set the reference vp supply (vpref) to 5.0 v. 3. enable battery compensation (battcmp). the cs43l22 automatically adjusts the output level as the battery discharges. refer to figure 11 on page 28 . in this example, the vp supply changes over a wide range, illustrati ng the accuracy of the cs43l22?s battery compensation. pin speaker output spkmono=0 spkmono=1 spkswap=0 spkswap=1 spkswap=0 spkswap=1 4 spkouta+ spkoutb+ spkouta+ spkoutb+ 6 spkouta- spkoutb- spkouta+ spkoutb+ 7 spkoutb+ spkouta+ spkouta- spkoutb- 9 spkoutb- spkouta- spkouta- spkoutb- referenced contro l register location spkmono.......................... spkswap........................... ?speaker mono control? on page 46 ?speaker channel swap? on page 45
28 ds792f2 cs43l22 confidential draft 3/4/10 referenced control register location vpref ................................ spkxvol ............................ ?vp reference? on page 57 ?speaker volume control? on page 52 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 uncompensated pwm output level battery compensated pwm output level vp supply (v) pwm output level (db) figure 11. battery compensation
ds792f2 29 cs43l22 confidential draft 3/4/10 4.6 serial port clocking the cs43l22 serial audio interface port operates either as a slave or master, determined by the m/s bit. it accepts externally generated clocks in slave mo de and will generate syn chronous clocks derived from an input master clock (mclk) in master mode. refer to th e tables below for the required setting in register 05h and 06h associated with a given mclk and sample rate. referenced control register location m/s ................................... register 05h...................... register 06h...................... ?master/slave mode? on page 40 ?clocking control (address 05h)? on page 38 ?interface control 1 (address 06h)? on page 40 mclk (mhz) sample rate, fs (khz) speed[1:0] (auto=?0?b) 32kgroup videoclk ratio[1:0] mclkdiv2 12.2880 8.0000 11 1 0 00 0 12.0000 11 0 0 00 0 16.0000 10 1 0 00 0 24.0000 10 0 0 00 0 32.0000 01 1 0 00 0 48.0000 01 0 0 00 0 96.0000 00 0 0 00 0 11.2896 11.0250 11 0 0 00 0 22.0500 10 0 0 00 0 44.1000 01 0 0 00 0 88.2000 00 0 0 00 0 18.4320 (slave mode only) 8.0000 11 1 0 00 0 12.0000 11 0 0 00 0 16.0000 10 1 0 00 0 24.0000 10 0 0 00 0 32.0000 01 1 0 00 0 48.0000 01 0 0 00 0 96.0000 00 0 0 00 0 16.9344 (slave mode only) *8.0182... 11 0 0 10 0 11.0250 11 0 0 00 0 22.0500 10 0 0 00 0 44.1000 01 0 0 00 0 88.2000 00 0 0 00 0 12.0000 8.0000 11 1 0 01 0 *11.0294... 11 0 0 11 0 12.0000 11 0 0 01 0 16.0000 10 1 0 01 0 *22.0588...10 0 0110 24.0000 10 0 0 01 0 32.0000 01 1 0 01 0 *44.1176...01 0 0110 48.0000 01 0 0 01 0 *88.2353...00 0 0110 96.0000 00 0 0 01 0 24.0000 8.0000 11 1 0 01 1 *11.0294... 11 0 0 11 1 12.0000 11 0 0 01 1 16.0000 10 1 0 01 1 *22.0588...10 0 0111 24.0000 10 0 0 01 1 32.0000 01 1 0 01 1 *44.1176...01 0 0111 48.0000 01 0 0 01 1 *88.2353...00 0 0111 96.0000 00 0 0 01 1
30 ds792f2 cs43l22 confidential draft 3/4/10 note: *the marked sample rate values are not exact representations of the actual frame clock frequency they have been truncated to 4 decimal places. th e exact value can be calculated by dividing the mclk being used by the desired mclk/lrck ratio. table 1. serial port clocking 4.7 digital interface formats the serial port operates in standard i2s, left-justifi ed, right-justified, or dsp mode digital interface formats with varying bit depths from 16 to 24. data is clocked into the dac on the rising edge of sclk. 27.0000 8.0000 11 1 1 01 0 12.0000 11 0 1 01 0 24.0000 10 0 1 01 0 32.0000 01 1 1 01 0 *44.1176... 01 0 1 11 0 48.0000 01 0 1 01 0 *11.0294... 11 0 1 11 0 *22.0588... 10 0 1 11 0 16.0000 10 1 1 01 0 mclk (mhz) sample rate, fs (khz) speed[1:0] (auto=?0?b) 32kgroup videoclk ratio[1:0] mclkdiv2 lrck sclk msb lsb msb lsb aouta left channel right channel sdin aoutb msb figure 12. i2s format lrck sclk msb lsb msb lsb left channel right channel sdin msb aouta aoutb figure 13. left-justified format lrck sclk msb lsb msb lsb left channel right channel sdin aouta aoutb audio word length (awl) figure 14. right-justified format\
ds792f2 31 cs43l22 confidential draft 3/4/10 4.7.1 dsp mode in dsp mode, the lrck acts as a frame sync for 2 data-packed words (left and right channel) input on sdin. the msb is input on the first sclk rising edge after the frame sync rising edge. the right channel immediately follows the left channel. 4.8 initialization the cs43l22 enters a power-down state upon initial power-up. the interpolatio n and decimation filters, delta-sigma and pwm modulators and control port regi sters are reset. the internal voltage reference, and switched-capacitor low-pass filters are powered down. the device will remain in the power-down state until the reset pin is brought high. the control port is ac- cessible once reset is high and the desired register settings can be loaded per the interface descriptions in the ?register description? on page 37 . once mclk is valid, the quiescent voltage, vq, and the internal voltage referenc e, filt+, will begin power- ing up to normal operation. the charge pump slowly powers up and charges the capacitors. power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut- ed state. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio and normal operation begins. 4.9 recommended power-up sequence 1. hold reset low until the power supplies are stable. 2. bring reset high. 3. the default state of the ?power ctl. 1? register (0x02) is 0x01. load the desired register settings while keeping the ?power ctl 1? register set to 0x01. 4. load the required initializ ation settings listed in section 4.11 . 5. apply mclk at the appropriate frequency, as discussed in section 4.6 . sclk may be applied or set to master at any time; lrck may only be applied or set to master while the pdn bit is set to 1. 6. set the ?power ctl 1? register (0x02) to 0x9e. 7. bring reset low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 4.10 recommended power-down sequence to minimize audible pops when turning off or placing the dac in standby, 1. mute the dac?s and pwm outputs. 2. disable soft ramp and zero cross volume transitions. 3. set the ?power ctl 1? register (0x02) to 0x9f. lrck sclk msb lsb sdin hp/line outb lsb left channel right channel msb lsb msb audio word length (awl) 1/fs hp/line outa figure 15. dsp mode format)
32 ds792f2 cs43l22 confidential draft 3/4/10 4. wait at least 100 s. the device will be fully powered down after this 100 s delay. prior to the removal of the master clock (mclk), this delay of at least 100 s must be implemented after step 3 to avoid premature disruption of the dac?s power down sequence. a disruption in the device?s power down sequence (i .e. removing the mclk signal before this 100 s delay) has consequences on both the headphone and pwm speaker amplifiers: the charge pump may stop abruptly, causing the headphone amplifiers to dr ive the outputs up to the +vhp supply. also, the last state of each ?+? and ?-? pw m output terminal before the premature removal of mclk could randomly be held at either vp or agnd. when this event occurs , it is possible for each pwm terminal to output opposing potentials, creating a dc so urce into the sp eaker voice coil. the disruption of the device?s power down sequence may also cause clicks and pops on the output of the dac?s as the modulator holds the last out put level before the mclk signal was removed. 5. mclk may be removed at this time. 6. to achieve the lowest operating quiescent curr ent, bring reset low. all control po rt registers will be reset to their default state. 4.11 required initialization settings various sections in the device must be adjusted by im plementing the initialization settings shown below after power-up sequence step 3 . all performance and power consumption measurements were taken with the following settings: 1. write 0x99 to register 0x00. 2. write 0x80 to register 0x47. 3. write ?1?b to bit 7 in register 0x32. 4. write ?0?b to bit 7 in register 0x32. 5. write 0x00 to register 0x00.
ds792f2 33 cs43l22 confidential draft 3/4/10 5. control port operation the control port is used to access the registers a llowing the cs43l22 to be configured for the desired op- erational modes and formats. the operation of the cont rol port may be complete ly asynchronous with re- spect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates using an i2c interf ace with the cs43l22 acti ng as a slave device. 5.1 i2c control sda is a bidirectional data line. data is clocked into and out of the devi ce by the clock, scl. the ad0 pin sets the lsb of the chip address; ?0? when connecte d to dgnd, ?1? when connec ted to vl. this pin may be driven by a host controller or directly connected to vl or dgnd. the ad0 pin state is sensed and the lsb of the chip address is set upon the release of the reset signal (a low-to-high transition). the signal timings for a read and write cycle are shown in figure 16 and figure 17 . a start condition is de- fined as a falling transition of sda wh ile the clock is high. a stop condition is defined as a rising transition of sda while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs43l22 after a start condition consis ts of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the address fi eld are fixed at 100101. to communi cate with the cs43l22, the chip ad- dress field, which is the first byte sent to the cs43l22, should match 1 00101 followed by the setting of the ad0 pin. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map), which selects the register to be read or written. if the operation is a read, the con- tents of the register point ed to by the map will be output. setting t he auto-increment bit in map allows suc- cessive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the cs43l22 after each input byte is read and is input to the cs43l22 from the microcon- troller after each transmitted byte. since the read operation c annot set the map, an aborted write operation is used as a preamble. as shown in figure 17 , the write operation is aborted after the ackno wledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 16. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 ad0 0 sda 1 0 0 1 0 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 17. control port timing, i2c read
34 ds792f2 cs43l22 confidential draft 3/4/10 send start condition. send 10010100 (chip address & write operation). receive acknowledge bit. send map byte, auto-increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10010101 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows succe ssive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 5.1.1 memory addr ess pointer (map) the map byte comes after the address byte and select s the register to be read or written. refer to the pseudo code above for implementation details. 5.1.1.1 map increment (incr) the device has map auto-increment ca pability enabled by the incr bit (t he msb) of the map. if incr is set to 0, map will stay constant for su ccessive i2c writes or reads. if incr is set to 1, map will auto-in- crement after each byte is read or written, allo wing block reads or writes of successive registers.
ds792f2 35 cs43l22 confidential draft 3/4/10 6. register qu ick reference default values are shown below the bit names. unless otherwise specified, all ?reserved? bits must maintain their default value. adr. function 7 6 5 4 3 2 1 0 01h id chipid4 chipid3 chipid2 chipid1 chipid0 revid2 revid1 revid0 p37 111 00xx x 02h power ctl 1 pdn7 pdn6 pdn5 pdn4 pdn3 pdn2 pdn1 pdn0 p37 0 0 0 0 000 1 03h reserved reserved reserved reserved rese rved reserved reserved reserved reserved 0 0 0 0 011 1 04h power ctl 2 pdn_hpb1 pdn_hpb0 pdn_hpa1 pdn_hpa0 pdn_spkb1 pdn_spkb0 pdn_spka1 pdn_spka0 p38 0 0 0 0 010 1 05h clocking ctl auto speed1 speed0 32kgroup videoclk ratio1 ratio0 mclkdiv2 p38 1 0 1 0 000 0 06h interface ctl 1 m/s inv_sclk reserved dsp dacdif1 dacdif0 awl1 awl0 p40 0 0 0 0 000 0 07h interface ctl 2 reserved sclk=mclk reserved reserved inv_swch reserved reserved reserved p41 0 0 0 0 000 0 08h passthrough a select reserved reserved reserved reserved passasel4 passasel3 passasel2 passasel1 p42 1 0 0 0 000 1 09h passthrough b select reserved reserved reserved reserved passbsel4 passbsel3 passbsel2 passbsel1 p42 1 0 0 0 000 1 0ah analog zc and sr settings reserved reserved reserved reserved anlgsftb anlgzcb anlgsfta anlgzca p42 1 0 1 0 010 1 0bh reserved reserved reserved reserved res erved reserved reserved reserved reserved 0 0 0 0 000 0 0ch passthrough gang control passb=a reserved reserved reserved res erved reserved reserved reserved p42 0 0 0 0 000 0 0dh playback ctl 1 hpgain2 hpgain1 hpgain0 pl ybckb=a inv_pcmb inv_pcma mstbmute mstamute p43 0 1 1 0 000 0 0eh misc. ctl passthrub passthrua passbmut e passamute freeze deemph digsft digzc p44 0 0 0 0 001 0 0fh playback ctl 2 hpbmute hpamute spkbmu te spkamute spkb=a spkswap spkmono mute50/50 p45 000 00 00 10h- reserved reserved reserved reserved rese rved reserved reserved reserved reserved 13h 0 0 0 0 0 0 0 0 14h passthrough a vol passavol7 passavol6 passavol5 passavol4 passavol3 passavol2 passavol1 passavol0 p46 0 0 0 0 000 0 15h passthrough b vol passbvol7 passbvol6 passbvol5 passbvol4 passbvol3 passbvol2 passbvol1 passbvol0 p46 0 0 0 0 000 0 16h- reserved reserved reserved reserved rese rved reserved reserved reserved reserved 17h 0 0 0 0 0 0 0 0 18h- reserved reserved reserved reserved rese rved reserved reserved reserved reserved 19h 1 0 0 0 0 0 0 0 1ah pcma vol pcmamute pcmavol6 pcmavol5 pcmavol4 pcmavol3 pcmavol2 pcmavol1 pcmavol0 p47 0 0 0 0 000 0 1bh pcmb vol pcmbmute pcmbvol6 pcmbvol5 pcmbvol4 pcmbvol3 pcmbvol2 pcmbvol1 pcmbvol0 p47 0 0 0 0 000 0 1ch beep freq, on time freq3 freq2 freq1 freq0 ontime3 ontime2 ontime1 ontime0 p47 0 0 0 0 000 0 1dh beep vol, off time offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 p48 0 0 0 0 000 0 1eh beep, tone cfg. beep1 beep0 beepmixdis treb_cf1 treb_cf0 bass_cf1 bass_cf0 tc_en p49 0 0 0 0 000 0 1fh tone ctl treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 p50 1 0 0 0 100 0
36 ds792f2 cs43l22 confidential draft 3/4/10 20h master a vol mstavol7 mstavol6 mstavol5 mstavol4 mstavol3 mstavol2 mstavol1 mstavol0 p51 000 00000 21h master b vol mstbvol7 mstbvol6 mstbvol5 ms tbvol4 mstbvol3 mstbvol2 mstbvol1 mstbvol0 p51 000 00000 22h headphone a volume hpavol7 hpavol6 hpavol5 hpavol4 hpavol3 hpavol2 hpavol1 hpavol0 p51 000 00000 23h headphone b volume hpbvol7 hpbvol6 hpbvol5 hpbvol4 hpbvol3 hpbvol2 hpbvol1 hpbvol0 p51 000 00000 24h speaker a volume spkavol7 spkavol6 spkavol5 spkavol4 spkavol3 spkavol2 spkavol1 spkavol0 p52 000 00000 25h speaker b volume spkbvol7 spkbvol6 spkbvol5 spkbvol4 spkbvol3 spkbvol2 spkbvol1 spkbvol0 p52 000 00000 26h channel mixer & swap pcmaswp1 pcmaswp0 pcmbswp1 pcmbswp0 reserved reserved reserved reserved p52 000 00000 27h limit ctl 1, thresholds lmax2 lmax1 lmax0 cush2 cush1 cush0 limsrdis limzcdis p53 000 00000 28h limit ctl 2, release rate limit limit_all limrrate5 limrrate4 limrrate3 limrrate2 limrrate1 limrrate0 p54 011 11111 29h limiter attack rate reserved reserved limarate5 limarate4 limarate3 limarate2 limarate1 limarate0 p55 000 00000 2ah reserved reserved reserved reserved res erved reserved reserved reserved reserved 000 00000 2bh reserved reserved reserved reserved res erved reserved reserved reserved reserved 001 11111 2ch- reserved reserved reserved reserved re served reserved reserved reserved reserved 2dh 0 0 0 0 0 0 0 0 2eh overflow & clock status reserved spclkerr dspbovfl dspaovfl pcmaovfl pcmbovfl reserved reserved p55 000 00000 2fh battery com- pensation battcmp vpmonitor reserved reserv ed vpref3 vpref2 vpref1 vpref0 p56 000 00000 30h vp battery level vplvl7 vplvl6 vplvl5 vplvl4 vplvl3 vplvl2 vplvl1 vplvl0 p57 000 00000 31h speaker status reserved reserved spkashrt spkbshrt spkr/hp reserved reserved reserved p57 000 00000 32h reserved reserved reserved reserved res erved reserved reserved reserved reserved 001 11011 33h reserved reserved reserved reserved res erved reserved reserved reserved reserved 000 00000 34h charge pump frequency chgfreq3 chgfreq2 chgfreq 1 chgfreq0 reserved reserved reserved reserved p58 010 11111 adr. function 7 6 5 4 3 2 1 0
ds792f2 37 cs43l22 confidential draft 3/4/10 7. register description all registers are read/write except for the chip i.d. and revision register and interrupt status register which are read only. see the following bit definition tables for bit assi gnment information. the default state of each bit after a power-up sequence or reset is shown as shaded in the tabl e. unless otherwise specifie d, all ?reserved? bits must maintain their default value. 7.1 chip i.d. and revision register (address 01h) (read only) 7.1.1 chip i.d. (read only) i.d. code for the cs43l22. 7.1.2 chip revision (read only) cs43l22 revision level. 7.2 power control 1 (address 02h) 7.2.1 power down configures the power st ate of the cs43l22. note: 1. all states of pdn[7:0] not shown in the table are reserved. 76543210 chipid4 chipid3 chipi d2 chipid1 chipid0 revid2 revid1 revid0 chipid[4:0] device 11100 cs43l22 revid[2:0] revision level 000 a0 001 a1 010 b0 011 b1 76543210 pdn7 pdn6 pdn5 pdn4 pdn3 pdn2 pdn1 pdn0 pdn[7:0] status 0000 0001 powered down - same as setting 1001 1111 1001 1110 powered up 1001 1111 powered down - same as setting 0000 0001
38 ds792f2 cs43l22 confidential draft 3/4/10 7.3 power control 2 (address 04h) 7.3.1 headphone power control configures how the spk/hp_sw pin, 6, controls the power for the headphone am plifier. 7.3.2 speaker power control configures how the spk/hp_sw pin, 6, controls the power for the speaker amplifier. 7.4 clocking control (address 05h) 7.4.1 auto-detect configures the auto-detect circuitry for detecting the speed mode of the cs43l22 when operating as a slave. notes: 1. the speed[1:0] bits are igno red and speed is de termined by the mclk/lrck ratio. 2. when auto is disabled and the cs43l22 operates in master mode, the mclkdiv2 bit is ignored. 3. certain sample and mclk fre quencies require setting the speed [1:0] bits, the 32k_group bit ( ?32khz sample rate group? on page 39 ) and/or the videoclk bit ( ?27 mhz video clock? on page 39 ) and ratio[1:0] bits ( ?internal mclk/lrck ratio? on page 39 ). low sample rates may also affect dynamic range performance in the typical aud io band. refer to the referenced application for more information. 76543210 pdn_hpb1 pdn_hpb0 pdn_hpa1 pdn_hp a0 pdn_spkb1 pdn_spkb0 pdn_spka1 pdn_spka0 pdn_hpx[1:0] headphone status 00 headphone channel is on when the spk/hp_sw pin, 6, is lo. headphone channel is off when the spk/hp_sw pin, 6, is hi. 01 headphone channel is on when the spk/hp_sw pin, 6, is hi. headphone channel is off when the spk/hp_sw pin, 6, is lo. 10 headphone channel is always on. 11 headphone channel is always off. pdn_spkx[1:0] speaker status 00 speaker channel is on when the spk/hp_sw pin, 6, is lo. speaker channel is off when the spk/hp_sw pin, 6, is hi. 01 speaker channel is on when the spk/hp_sw pin, 6, is hi. speaker channel is off when the spk/hp_sw pin, 6, is lo. 10 speaker channel is always on. 11 speaker channel is always off. 76543210 auto speed1 speed0 32k_group videoclk ratio1 ratio0 mclkdiv2 auto auto-detection of speed mode 0 disabled 1 enabled application: ?serial port clocking? on page 29
ds792f2 39 cs43l22 confidential draft 3/4/10 7.4.2 speed mode configures the speed mode of the dac in slave mode and sets the appropriate mclk divide ratio for lrck and sclk in master mode. notes: 1. slave/master mode is determined by the m/s bit in ?master/slave mode? on page 40 . 2. certain sample and mclk freq uencies require setting the speed [1:0] bits, the 32k_group bit ( ?32khz sample rate group? on page 39 ) and/or the videoclk bit ( ?27 mhz video clock? on page 39 ) and ratio[1:0] bits ( ?internal mclk/lrck ratio? on page 39 ). low sample rates may also affect dynamic range performance in the typical a udio band. refer to the referenced application for more information. 3. these bits are ignored when the auto bit ( ?auto-detect? on page 38 ) is enabled. 7.4.3 32khz sample rate group specifies whether or not the input/output sa mple rate is 8 khz, 16 khz or 32 khz. 7.4.4 27 mhz video clock specifies whether or not the exte rnal mclk frequency is 27 mhz 7.4.5 internal mclk/lrck ratio configures the internal mclk/lrck ratio. speed[1:0] slave mode master mode serial port speed mclk/lrck ratio sclk/lrck ratio 00 double-speed mode (dsm - 50 khz -100 khz fs) 512 64 01 single-speed mode (ssm - 4 khz -50 khz fs) 256 64 10 half-speed mode (hsm - 12.5khz -25 khz fs) 128 64 11 quarter-speed mode (qsm - 4 khz -12.5 khz fs) 128 64 application: ?serial port clocking? on page 29 32kgroup 8 khz, 16 khz or 32 khz sample rate? 0 no 1yes application: ?serial port clocking? on page 29 videoclk 27 mhz mclk? 0 no 1yes application: ?serial port clocking? on page 29 ratio[1:0] internal mclk cycles per lrck sclk/lrck ratio in master mode 00 128 64 01 125 62 10 132 66 11 136 68 application: ?serial port clocking? on page 29
40 ds792f2 cs43l22 confidential draft 3/4/10 7.4.6 mclk divide by 2 divides the input mclk by 2 pr ior to all internal circuitry. note: in slave mode, this bit is ignored when the auto bit ( ?auto-detect? on page 38 ) is disabled. 7.5 interface control 1 (address 06h) 7.5.1 master/slave mode configures the serial port i/o clocking. 7.5.2 sclk polarity configures the polarity of the sclk signal. 7.5.3 dsp mode configures a data-packed interface format for the dac. notes: 1. select the audio word length using the awl[1:0] bits ( ?audio word length? on page 41 ). 2. the interface format for the da c must be set to ?left-justifie d? when dsp mode is enabled. 7.5.4 dac interface format configures the digital interface format for data on sdin. note: select the audio word leng th for right justified using the awl[1:0] bits ( ?audio word length? on page 41 ). mclkdiv2 mclk signal into dac 0 no divide 1 divided by 2 application: ?serial port clocking? on page 29 76543210 m/s inv_sclk reserved dsp dacdif1 dacdif0 awl1 awl0 m/s serial port clocks 0 slave (input only) 1 master (output only) inv_sclk sclk polarity 0 not inverted 1 inverted dsp dsp mode 0 disabled 1 enabled application: ?dsp mode? on page 31 dacdif[1:0] dac interface format 00 left justified, up to 24-bit data 01 i2s, up to 24-bit data 10 right justified 11 reserved application: ?digital interface formats? on page 30
ds792f2 41 cs43l22 confidential draft 3/4/10 7.5.5 audio word length configures the audio sample word length used for the data into sdin. note: when the internal mclk/lrck ratio is set to 125 in master mode, the 32-bit data width option for dsp mode is not valid unless sclk=mclk. 7.6 interface contro l 2 (address 07h) 7.6.1 sclk equals mclk configures the sclk signal source for master mode. note: this bit is only valid for mclk = 12.0000 mhz. 7.6.2 speaker/headphone switch invert determines the control signal po larity of the spk/hp_sw pin. awl[1:0] audio word length dsp mode right justified 00 32-bit data 24-bit data 01 24-bit data 20-bit data 10 20-bit data 18-bit data 11 16-bit data 16-bit data application: ?dsp mode? on page 31 76543 2 1 0 reserved sclk=mclk reserved reserved inv_swch reserved reserved reserved sclk=mclk output sclk 0 re-timed signal, synchronously derived from mclk 1 non-retimed, mclk signal inv_swch spk/hp_sw pin 6 control 0 not inverted 1 inverted
42 ds792f2 cs43l22 confidential draft 3/4/10 7.7 passthrough x select: passa (address 08h), passb (address 09h) 7.7.1 passthrough input channel mapping selects one or sums/mixes the analog input signal into the passthrough amplifier. each bit of the passx_sel[4:1] word correspond s to individual channels (i .e. passx_sel1 selects ain1x, passx_sel2 selects ain2x, etc.). 7.8 analog zc and sr settings (address 0ah) 7.8.1 ch. x analog soft ramp configures an incremental volume ramp from the curr ent level to the new level at the specified rate. 7.8.2 ch. x analog zero cross configures when the signal level changes occur for the analog volume controls. note: if the signal does not en counter a zero crossing, the request ed volume change will occur after a timeout period of 1024 sample periods (approximately 10.7 ms at 48 khz sample rate). 7.9 passthrough gang control (address 0ch) 7.9.1 passthrough channe l b=a gang control configures independent or ganged control of the pa ssthrough channel settings. mute is not affected. 7 6 5 4 3210 reserved reserved reserved rese rved passasel4 passasel3 passasel2 passasel1 passxsel[4:1] selected input to passthrough channel x 00000 no inputs selected 00001 ain1x 00010 ain2x 00100 ain3x 01000 ain4x application: ?analog passthrough? on page 24 note: table does not show all possible combinations. 76543210 reserved reserved reserved reserved anlgsftb anlgzcb anlgsfta anlgzca anlgsftx volume changes affected analog volume controls 0 do not occur with a soft ramp passxvol[7:0] ( ?passthrough x volume? on page 46 ) 1 occur with a soft ramp ramp rate: 1/2 db every 16 lrck cycles anlgzcx volume changes affected analog volume controls 0 do not occur on a zero cross- ing passxvol[7:0] ( ?passthrough x volume? on page 46 ) 1 occur on a zero crossing 76543210 passb=a reserved reserved reserved reserved reserved reserved reserved passb=a single volume control 0 disabled 1 enabled
ds792f2 43 cs43l22 confidential draft 3/4/10 7.10 playback control 1 (address 0dh) 7.10.1 headphone analog gain selects the gain multiplier for the headphone/line outputs. note: refer to ?headphone output power characteristics? on page 14 and ?headphone output power characteristics? on page 14 . 7.10.2 playback volume setting b=a configures independent or ganged volume control of all playback channels. mute is not affected. 7.10.3 invert pcm signal polarity configures the polarity of the digital input signal. 7.10.4 master playback mute configures a digital mute on the master volume control for channel x. note: the muting function is affected by the digsft ( ?digital soft ramp? on page 44 ) and digzc ( ?digital zero cross? on page 45 ) bits. 76543210 hpgain2 hpgain1 hpgain0 plybckb=a inv_pcmb inv_pcma mstbmute mstamute hpgain[2:0] headphone/line gain setting (g) 000 0.3959 001 0.4571 010 0.5111 011 0.6047 100 0.7099 101 0.8399 110 1.000 111 1.1430 plybckb=a single volume control for all playback channels 0 disabled 1 enabled inv_pcmx pcm signal polarity 0 not inverted 1 inverted mstxmute master mute 0 not inverted 1 inverted
44 ds792f2 cs43l22 confidential draft 3/4/10 7.11 miscellaneous controls (address 0eh) 7.11.1 passthrough analog configures an analog passthrough from the analog inputs to the headphone/line outputs. 7.11.2 passthrough mute configures an analog mute on the channel x analog in to analog out passthrough. 7.11.3 freeze registers configures a hold on all register settings. 7.11.4 hp/speaker de-emphasis configures a 15 s/50 s digital de-emphasis filter response on the headphone/line and speaker outputs . 7.11.5 digital soft ramp configures an incremental volume ramp from the curr ent level to the new level at the specified rate. 76543210 passthrub passthrua passbmute passamute freeze deemph digsft digzc passthrux analog in routed to hp/line output 0 disabled 1 enabled passxmute passthrough mute 0 disabled 1 enabled freeze control port status 0 register changes take effect immediately 1 modifications may be made to all control port register s without the changes taking effect until after the freeze is disabled. deemphasis control port status 0 disabled 1 enabled digsft volume changes affected digital volume controls 0 does not occur with a soft ramp mstxmute ( ?master playback mute? on page 43 ), hpxmute, spkxmute ( ?playback control 2 (address 0fh)? on page 45 ), pcmxmute, pcmxvol[7:0] ( ?pcm channel x volume? on page 47 ), mstxvol[7:0] ( ?master volume control? on page 51 ), hpxvol[7:0] ( ?headphone volume control? on page 51 ), spkxvol[7:0] ( ?speaker volume control? on page 52 ), 1 occurs with a soft ramp ramp rate: 1/8 db every lrck cycle
ds792f2 45 cs43l22 confidential draft 3/4/10 7.11.6 digital zero cross configures when the signal level changes occur for the digital volume controls. notes: 1. if the signal does not encounter a zero crossing , the requested volume change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 khz sample rate). 2. the zero cross function is independently monitored and implemented for each channel. 3. the dis_limsft bit ( ?limiter soft ramp disable? on page 53 ) is ignored when zero cross is enabled. 7.12 playback control 2 (address 0fh) 7.12.1 headphone mute configures a digital mute on headphone channel x. 7.12.2 speaker mute configures a digital mute on speaker channel x. 7.12.3 speaker volume setting b=a configures independent or ganged volume control of the speaker volume. mute is not affected. 7.12.4 speaker channel swap configures a channel swap on the speaker channels. digzc volume changes affected digital volume controls 0 do not occur on a zero cross- ing mstxmute ( ?master playback mute? on page 43 ), hpxmute, spkxmute ( ?playback control 2 (address 0fh)? on page 45 ), pcmxmute, pcmxvol[7:0] ( ?pcm channel x volume? on page 47 ), mstxvol[7:0] ( ?master volume control? on page 51 ), hpxvol[7:0] ( ?headphone volume control? on page 51 ), spkxvol[7:0] ( ?speaker volume control? on page 52 ), 1 occur on a zero crossing 76543210 hpbmute hpamute spkbmute spkamut e spkb=a spkswap spkmono mute50/50 hpxmute headphone mute 0 disabled 1 enabled spkxmute speaker mute 0 disabled 1 enabled spkb=a single volume control for the speaker channel 0 disabled 1 enabled spkswap speaker output 0 channel a 1 channel b application: ?mono speaker output configuration? on page 27
46 ds792f2 cs43l22 confidential draft 3/4/10 7.12.5 speaker mono control configures a parallel full bridge output for the speaker channels. 7.12.6 speaker mute 50/50 control configures how the speaker channels mute. 7.13 passthrough x volume: passavol (a ddress 14h) & passbvol (address 15h) 7.13.1 passthrough x volume sets the volume/gain of the analog input si gnal routed to the headphone/line output. notes: 1. this register is igno red when the passthrux bit ( ?passthrough analog? on page 44 ) is disabled. 2. the step size may deviate from 0.5 db at settings below -40 db. code settings 0x95, 0xa1, 0xad and 0xb9 are not guaranteed to be monotonic. spkmono parallel full bridge output 0 disabled 1 enabled application: ?mono speaker output configuration? on page 27 mute50/50 speaker mute 50/50 0 disabled; the pwm amplifiers outputs modulated silence when spkxmute is enabled. 1 enabled; the pwm amplifiers switch at an exact 50%- duty-cycle signal (not mo dulated) when spkxmute is enabled. 76543210 passxvol7 passxvol6 passxvol5 passxvol4 passxvol3 passxvol2 passxvol1 passxvol0 passxvol[7:0] gain 0111 1111 12 db ... ... 0001 1000 12 db ... ... 0000 0001 +0.5 db 0000 0000 0 db 11111 1111 -0.5 db ... ... 1000 1000 -60.0 db ... ... 1000 0000 -60.0 db step size: 0.5 db (approximate) application: ?passthrough analog? on page 44
ds792f2 47 cs43l22 confidential draft 3/4/10 7.14 pcmx volume: pcma (addr ess 1ah) & pcmb (address 1bh) 7.14.1 pcm channel x mute configures a digital mute on the pcm data from the serial data input (sdin) to the dsp. 7.14.2 pcm channel x volume sets the volume/gain of the pc m data from the serial data input (sdin) to the dsp. 7.15 beep frequency & on time (address 1ch) 7.15.1 beep frequency sets the frequency of the beep signal. 7 6543210 pcmxmute pcmxvol6 pcmxvol5 pcmxvol4 pcmxvol3 pcmxvol2 pcmxvol1 pcmxvol0 pcmxmute pcm mute 0 disabled 1 enabled pcmxvol[6:0] volume 001 1000 +12.0 db ... ... 000 0001 +0.5 db 000 0000 0 db 111 1111 -0.5 db ... ... 001 1001 -51.5 db step size: 0.5 db 76543210 freq3 freq2 freq1 freq0 onti me3 ontime2 ontime1 ontime0 freq[3:0] frequency (fs = 12, 24, 48 or 96 khz) pitch 0000 260.87 hz c4 0001 521.74 hz c5 0010 585.37 hz d5 0011 666.67 hz e5 0100 705.88 hz f5 0101 774.19 hz g5 0110 888.89 hz a5 0111 1000.00 hz b5 1000 1043.48 hz c6 1001 1200.00 hz d6 1010 1333.33 hz e6 1011 1411.76 hz f6 1100 1600.00 hz g6 1101 1714.29 hz a6 1110 2000.00 hz b6 1111 2181.82 hz c7 application: ?beep generator? on page 22
48 ds792f2 cs43l22 confidential draft 3/4/10 notes: 1. this setting must not change when beep is enabled. 2. beep frequency will scale directly with sample rate, fs, but is fixe d at the nominal fs within each speed mode. 7.15.2 beep on time sets the on duration of the beep signal. notes: 1. this setting must not change when beep is enabled. 2. beep on time will scale inversely with sample rate, fs , but is fixed at the nominal fs within each speed mode. 7.16 beep volume & of f time (address 1dh) 7.16.1 beep off time sets the off duration of the beep signal. ontime[3:0] on time (fs = 12, 24, 48 or 96 khz) 0000 ~86 ms 0001 ~430 ms 0010 ~780 ms 0011 ~1.20 s 0100 ~1.50 s 0101 ~1.80 s 0110 ~2.20 s 0111 ~2.50 s 1000 ~2.80 s 1001 ~3.20 s 1010 ~3.50 s 1011 ~3.80 s 1100 ~4.20 s 1101 ~4.50 s 1110 ~4.80 s 1111 ~5.20 s application: ?beep generator? on page 22 76543210 offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 offtime[2:0] off time (fs = 48 or 96 khz) 000 ~1.23 s 001 ~2.58 s 010 ~3.90 s 011 ~5.20 s 100 ~6.60 s 101 ~8.05 s 110 ~9.35 s 111 ~10.80 s application: ?beep generator? on page 22
ds792f2 49 cs43l22 confidential draft 3/4/10 notes: 1. this setting must not ch ange when beep is enabled. 2. beep off time will scale inversely wit h sample rate, fs, but is fixed at the nominal fs within each speed mode. 7.16.2 beep volume sets the volume of the beep signal. note: this setting must not ch ange when beep is enabled. 7.17 beep & tone configuration (address 1eh) 7.17.1 beep configuration configures a beep mixed with the hp/line and spk output. notes: 1. when used in analog pass through mode, the output alternates between the signal from the passthrough amplifier and the beep signal. the beep signal does not mix with the analog signal from the passthrough amplifier. 2. re-engaging the beep befor e it has completed its initial cycle w ill cause the beep signal to remain on for the maximum ontime duration. 7.17.2 beep mix disable configures how the beep mixes with the serial data input. note: this setting must not ch ange when beep is enabled. beepvol[4:0] gain 00110 +6.0 db 00000 -6 db 11111 -8 db 11110 -10 db 00111 -56 db step size: 2 db application: ?beep generator? on page 22 76543210 beep1 beep0 beepmixdis trebcf1 trebcf0 basscf1 basscf0 tcen beep[1:0] beep occurrence 00 off 01 single 10 multiple 11 continuous application: ?beep generator? on page 22 beepmixdis beep output to hp/line and speaker 0 mix enabled; the beep signal mixes with the digital signal from the serial data input. 1 mix disabled; the output alternates between the signal from the serial data input and the beep signal. the beep signal does not mix with the digita l signal from the serial data input. application: ?beep generator? on page 22
50 ds792f2 cs43l22 confidential draft 3/4/10 7.17.3 treble corner frequency sets the corner frequency (-3 db point) for the treble shelving filter. 7.17.4 bass corner frequency sets the corner frequency (-3 db point) for the bass shelving filter. 7.17.5 tone control enable configures the treble and bass activation. 7.18 tone contro l (address 1fh) 7.18.1 treble gain sets the gain of the treble shelving filter. trebcf[1:0] treble corner frequency setting 00 5 khz 01 7 khz 10 10 khz 11 15 khz basscf[1:0] bass corner frequency setting 00 50 hz 01 100 hz 10 200 hz 11 250 hz tcen bass and treble control 0 disabled 1 enabled application: ?beep generator? on page 22 76543210 treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 treb[3:0] gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db step size: 1.5 db
ds792f2 51 cs43l22 confidential draft 3/4/10 7.18.2 bass gain sets the gain of the bass shelving filter. 7.19 master volume control: ms ta (address 20h) & mstb (address 21h) 7.19.1 master volume control sets the volume of the signal out the dsp. 7.20 headphone volume control: hpa (address 22h) & hpb (address 23h) 7.20.1 headphone volume control sets the volume of the signal out the dac. treb[3:0] gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db step size: 1.5 db 76543210 mstxvol7 mstxvol6 mstxvol5 mstxvol4 mstxvol3 mstxvol2 mstxvol1 mstxvol0 mstxvol[7:0] master volume 0001 1000 +12.0 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -102 db 0001 1001 -102 db step size: 0.5 db 76543210 hpxvol7 hpxvol6 hpxvol5 hpxvol4 hpxvol3 hpxvol2 hpxvol1 hpxvol0 hpxvol[7:0] headphone volume 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -96.0 db 0000 0001 muted step size: 0.5 db
52 ds792f2 cs43l22 confidential draft 3/4/10 7.21 speaker volume control: spka (address 24h) & spkb (address 25h) 7.21.1 speaker volume control sets the volume of the signal out the pwm modulator. note: the maximum step size error is +/-0.15 db. 7.22 pcm channel swap (address 26h) 7.22.1 pcm channel swap configures a mix/swap of the pcm data to the headphone/line or speaker outputs. 76543210 spkxvol7 spkxvol6 spkxvol5 spkxvol4 spkxvol3 spkxvol2 spkxvol1 spkxvol0 spkxvol[7:0] speaker volume 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0100 0000 -96.0 db 0000 0001 muted step size: 0.5 db 76543210 pcmaswp1 pcmaswp0 pcmbswp1 pcmbswp0 reserved reserved reserved reserved pcmxswp[1:0] pcm to hp/lineouta pcm to hp/lineoutb 00 left right 01 (left + right)/2 (left + right)/2 10 11 right left
ds792f2 53 cs43l22 confidential draft 3/4/10 7.23 limiter control 1, min/ max thresholds (address 27h) 7.23.1 limiter maximum threshold sets the maximum level, be low full scale, at which to limit and a ttenuate the output signal at the attack rate (limarate - ?limiter release rate? on page 54 ). note: bass, treble and digital gain settings that bo ost the signal beyond the maximum threshold may trigger an attack. 7.23.2 limiter cushion threshold sets the minimum level at which to disengage the limi ter?s attenuation at the release rate (limrrate - ?limiter release rate? on page 54 ) until levels lie between the lmax and cush thresholds. note: this setting is usually set sli ghtly below the lmax threshold. 7.23.3 limiter soft ramp disable configures an override of the digital soft ramp setting. note: this bit is ignored when the digzc ( ?digital zero cross? on page 45 ) is enabled. 76543210 lmax2 lmax1 lmax0 cush2 cush1 cush0 limsrdis limzcdis lmax[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?limiter? on page 22 cush[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?limiter? on page 22 limsrdis limiter soft ramp disable 0 off; limiter attack rate is dictated by the digsft ( ?digital soft ramp? on page 44 ) setting 1 on; limiter volume changes take effect in one step, regardless of the digsft setting. application: ?limiter? on page 22
54 ds792f2 cs43l22 confidential draft 3/4/10 7.23.4 limiter zero cross disable configures an override of the digital zero cross setting. 7.24 limiter control 2, release rate (address 28h) 7.24.1 peak detect and limiter configures the peak detect and limiter circuitry. 7.24.2 peak signal limit all channels sets how channels are attenuated when the limiter is enabled. 7.24.3 limiter release rate sets the rate at which the limiter releases the digita l attenuation from levels below the cush[2:0] thresh- old ( ?limiter cushion th reshold? on page 53 ) and returns the analog output level to the mstxvol[7:0] ( ?master volume control? on page 51 ) setting. note: the limiter release rate is user-selectable but is also a function of the sampling frequency, fs, and the digsft ( ?digital soft ramp? on page 44 ) and digzc ( ?digital zero cross? on page 45 ) setting. limzcdis limiter zero cross disable 0 off; limiter attack rate is dictated by the digzc ( ?digital zero cross? on page 45 ) setting 1 on; limiter volume changes take effect in one step, regardless of the digzc setting. application: ?limiter? on page 22 76543210 limit limit_all limrrate5 limrrate4 limrrate3 limrrate2 limrrate1 limrrate0 limit limiter status 0 disabled 1 enabled application: ?limiter? on page 22 limit_all limiter action: 0 apply the necessary attenuation on a specific channel only when the signal amplitude on that specific chan- nel rises above lmax. remove attenuation on a specific c hannel only when the signal amplitude on that specific channel falls below cush. 1 apply the necessary attenuation on both channels w hen the signal amplitude on any one channel rises above lmax. remove attenuation on both channels only when the signal amplitude on both channels fall below cush. application: ?limiter? on page 22 limrrate[5:0] release time 00 0000 fastest release 11 1111 slowest release application: ?limiter? on page 22
ds792f2 55 cs43l22 confidential draft 3/4/10 7.25 limiter attack rate (address 29h) 7.25.1 limiter attack rate sets the rate at which the limiter applies digital attenuation from le vels above the max[2:0] threshold ( ?limiter maximum threshold? on page 53 ). note: the limiter attack rate is user-selectable but is also a function of the sampling frequency, fs, and the digsft ( ?digital soft ramp? on page 44 ) and digzc ( ?digital zero cross? on page 45 ) setting unless the respective disable bit ( ?limiter soft ramp disable? on page 53 or ?limiter zero cross disable? on page 54 ) is enabled. 7.26 status (address 2eh) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated erro r condition has not occurred since the last reading of the register. reading the register resets all bits to 0. 7.26.1 serial port cl ock error (read only) indicates the status of the mclk to lrck ratio. note: on initial power up and applicatio n of clocks, this bit will report ?1 ?b as the serial port re-synchro- nizes. 7.26.2 dsp engine overflow (read only) indicates the over-range status in the dsp data path. 76543210 reserved reserved limarate5 limarate4 li marate3 limarate2 limarate1 limarate0 limarate[5:0] attack time 00 0000 fastest attack 11 1111 slowest attack application: ?limiter? on page 22 76543210 reserved spclkerr dspaovfl dspbovfl pcmaovfl pcmbovfl reserved reserved spclkerr serial port clock status: 0 mclk/lrck ratio is valid. 1 mclk/lrck ratio is not valid. application: ?serial port clocking? on page 29 dspxovfl dsp overflow status: 0 no digital clipping has occurred in the data path after the dsp. 1 digital clipping has occurred in the data path after the dsp. application: ?dsp engine? on page 21
56 ds792f2 cs43l22 confidential draft 3/4/10 7.26.3 pcmx overflow (read only) indicates the over-range status in the pcm data path. 7.27 battery compensation (address 2fh) 7.27.1 battery compensation configures automatic adjustment of the speake r volume when vp deviat es from vpref[3:0]. 7.27.2 vp monitor configures the internal adc that monitors the vp voltage level. notes: 1. the internal adc that monitors the vp supply is enabled automatically when battcmp is enabled, re- gardless of the vpmonitor setting. conversely, when battcmp is disabled, the adc may be en- abled by enabling vpmonitor; this provides a convenient battery monitor without enabling battery compensation. 2. when enabled, vpmonitor remains enabl ed regardless of the pdn bit setting. pcmxovfl pcm overflow status: 0 no digital clipping has occurred in the data path of the pcm ( ?pcm channel x volume? on page 47 ) of the dsp. 1 digital clipping has occurred in the data path of the pcm of the dsp. application: ?dsp engine? on page 21 76543210 battcmp vpmonitor reserved rese rved vpref3 vpref2 vpref1 vpref0 battcmp automatic battery compensation 0 disabled 1 enabled application: ?maintaining a desired output level? on page 27 vpmonitor vp adc status 0 disabled 1 enabled
ds792f2 57 cs43l22 confidential draft 3/4/10 7.27.3 vp reference sets the desired vp reference used for battery compensation. 7.28 vp battery level (address 30h) (read only) 7.28.1 vp voltage level (read only) indicates the unsigned vp voltage level. 7.29 speaker status (add ress 31h) (read only) 7.29.1 speaker current load status (read only) indicates whether or not any of the sp eaker outputs is shorted to ground. vpref[3:0] desired vp used to calculate the required attenuation on the speaker output: (for va = 1.8 v) 0000 1.5 v 0001 2.0 v 0010 2.5 v 0011 3.0 v 0100 3.5 v 0101 4.0 v 0110 4.5 v 0111 5.0 v (for va = 2.5 v) 1000 1.5 v 1001 2.0 v 1010 2.5 v 1011 3.0 v 1100 3.5 v 1101 4.0 v 1110 4.5 v 1111 5.0 v application: ?vp battery compensation? on page 27 76543210 vplvl7 vplvl6 vplvl5 vplvl4 vplvl3 vplvl2 vplvl1 vplvl0 vplvl[7:0] vp voltage ... 0101 1110 3.0 v (for va = 2.0 v); apply formula using actual va voltage to calculate vp voltage. ... 0111 0010 3.7 v (for va = 2.0 v); apply formula using actual va voltage to calculate vp voltage. ... formula: vp voltage = (binary representation of vplvl[7:0]) * va / 63.3 76543210 reserved reserved spkashrt spkbshrt spkr/hp reserved reserved reserved spkxshrt speaker output load 0 no overload detected 1 overload detected
58 ds792f2 cs43l22 confidential draft 3/4/10 7.29.2 spkr/hp pin status (read only) indicates the status of the spkr/hp pin. 7.30 charge pump frequency (address 34h) 7.30.1 charge pump frequency sets the charge pump frequency on flyn and flyp. note: the headphone output thd+n pe rformance may be affected. spkr/hp pin state 0 pulled low 1 pulled high 76543210 chgfreq3 chgfreq2 chgfreq1 chgfreq0 r eserved reserved reserved reserved chgfreq[3:0] n 0000 0 ... 0101 5 ... 1111 15 formula: frequency = (64xfs)/(n+2)
ds792f2 59 cs43l22 confidential draft 3/4/10 8. analog performance plots 8.1 headphone thd+n versu s output power plots test conditions (unless otherwise specified): input test signal is a 997 hz sine wave; measurement band- width is 10 hz to 20 khz; fs = 48 khz. g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 18. thd+n vs. output power per channel at 1.8 v (16 load) vhp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 23 mw into single 16 and 46 mw into stereo 16 with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 19. thd+n vs. output power per channel at 2.5 v (16 load) vhp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 44 mw into single 16 and 88 mw into stereo 16 with thd+n = - 75 db).
60 ds792f2 cs43l22 confidential draft 3/4/10 g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 d b r a 0 60m 6m 12m 18m 24m 30m 36m 42m 48m 54m w figure 20. thd+n vs. output power per channel at 1.8 v (32 load) vhp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 22 mw into single 32 and 44 mw into stereo 32 with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d b r a 0 60m 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m w figure 21. thd+n vs. output power per channel at 2.5 v (32 load) vhp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 42 mw into single 32 and 84 mw into stereo 32 with thd+n = - 75 db).
ds792f2 61 cs43l22 confidential draft 3/4/10 9. example system clock frequencies *the?mclkdiv2? bit must be enabled. 9.1 auto detect enabled 9.2 auto detect disabled sample rate lrck (khz) mclk (mhz) 1024x 1536x 2048x* 3072x* 8 8.1920 12.2880 16.3840 24.5760 11.025 11.2896 16.9344 22.5792 33.8688 12 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x* 1536x* 16 8.1920 12.2880 16.3840 24.5760 22.05 11.2896 16.9344 22.5792 33.8688 24 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x* 768x* 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x* 384x* 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x 1536x 2048x 3072x 8 - 6.1440 8.1920 12.2880 16.3840 24.5760 11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688 12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1536x 16 - 6.1440 8.1920 12.2880 16.3840 24.5760 22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688 24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
62 ds792f2 cs43l22 confidential draft 3/4/10 10.pcb layout considerations 10.1 power supply, grounding as with any high-resolution converter, the cs43l22 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 1 on page 9 shows the recommended power arrangements, with va and vhp connected to cl ean supplies vd, which powers the digital circuitry, may be run from the system logic supply. alternativel y, vd may be powered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. decoupling capacitors shou ld be as close to the pins of the cs43l22 as pos- sible. the low value ceramic capacitor should be cl osest to the pin and should be mounted on the same side of the board as the cs43l22 to minimize inductance effects. all signals, especially clocks, should be kept away fr om the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the vq decoupling capaci tors, particularly the 0. 1 f, must be positioned to minimize the electrical path from agnd. the cdb43l 22 evaluation board demonstrates the optimum layout and power supply arrangements. 10.2 qfn thermal pad the cs43l22 is available in a compact qfn package. the underside of the qfn package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of vias should be used to connect this copper pad to one or more larger ground planes on other pcb layers. in split ground systems, it is recommended that this thermal pad be connected to agnd for best perfor- mance. the cs43l22 evaluation board demonstrates the optimum thermal pad and via configuration.
ds792f2 63 cs43l22 confidential draft 3/4/10 11.digital filter plots figure 22. passband ripple figure 23. stopband figure 24. dac transition band figure 25. transition band (detail)
64 ds792f2 cs43l22 confidential draft 3/4/10 12.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specif ied band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement te chnique has been accepted by the au dio engineering society, aes17-1991, and the electronic industries as sociation of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified band width (typically 10 hz to 20 khz), including di stortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chann el pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain drift the change in gain value with temperature. units in ppm/c.
ds792f2 65 cs43l22 confidential draft 3/4/10 13.package dimensions 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0394 -- -- 1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1 , 2 d 0.2362 bsc 6.00 bsc 1 d2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1 e 0.2362 bsc 6.00 bsc 1 e2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja ja - - 44 19 - - c/watt c/watt 40l qfn (6 x 6 mm body) package drawing e b a a1 pin #1 identifier ? 0.50 0.10 laser mar ki n g e 2.00 ref d2 l pin #1 corner 2.00 ref e2 d
66 ds792f2 cs43l22 confidential draft 3/4/10 14.ordering information 15.references 1. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semiconductors.philips.com 16.revision history product description package pb-free grade temp range container order # cs43l22 low-power stereo dac w/hp and speaker amps for portable apps 40l-qfn yes commercial -40 to +85 c rail cs43l22-cnz tape & reel CS43L22-CNZR cdb43l22 cs43l22 evaluation board - no - - - cdb43l22 revision changes f2 added ad0 characteristics to ?i/o pin characteristics? on page 8 . added a description of the ad0 pin to ?i2c control? on page 33 . added ad0 detail to figure 16. control port timing, i2c write on page 33 and figure 17. control port timing, i2c read on page 33 . updated the first paragraph in ?register quick reference? on page 35 and ?register description? on page 37 to allow for data sheet-specified cont rol-writes to re served registers. updated note 3 on page 11 . removed i2c address heading row from ?register quick reference? on page 35 . contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclusion of cirrus prod ucts in such applications is understood to be fully at the customer?s risk and cir- rus disclaims and makes no warranty, express, statutory or im plied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in su ch a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a trademark of philips semiconductor.

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